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Correctness and Efficiency Criteria for the Multi-Phase Task Model

Authors Rémi Meunier , Thomas Carle , Thierry Monteil

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Author Details

Rémi Meunier
  • IRIT, AUSY, INSA Toulouse, France
Thomas Carle
  • IRIT, Universite Toulouse 3 Paul Sabatier, CNRS, France
Thierry Monteil
  • IRIT, INSA Toulouse, CNRS, France

Funding

This work was supported by a grant overseen by the French National Research Agency (ANR) as part of the MeSCAliNe (ANR-21-CE25-0012) project.

Cite As Get BibTex

Rémi Meunier, Thomas Carle, and Thierry Monteil. Correctness and Efficiency Criteria for the Multi-Phase Task Model. In 34th Euromicro Conference on Real-Time Systems (ECRTS 2022). Leibniz International Proceedings in Informatics (LIPIcs), Volume 231, pp. 9:1-9:21, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2022) https://doi.org/10.4230/LIPIcs.ECRTS.2022.9

Abstract

This paper investigates how the multi-phase representation of real-time tasks impacts their implementation and the precision of the interference analysis in a multi-core context. In classical scheduling and interference analyses, tasks are represented as a single phase with a duration equal to their Worst-Case Execution Time (WCET) in isolation, annotated with their worst-case number of accesses. We propose a general formal definition of a task model in which tasks are represented as a sequence of such phases: the multi-phase model. We then provide a set of general correction criteria for the implementation of tasks represented in the multi-phase model, which is agnostic of the analysis method applied on the tasks. We also use the multi-phase model on an avionics case-study and study its impact on the interference analysis. Finally, we define a set of efficiency criteria using a statistical study of the most efficient multi-phase shapes.

Subject Classification

ACM Subject Classification
  • Computer systems organization → Real-time systems
  • Computer systems organization → Multicore architectures
  • Computer systems organization → Embedded software
Keywords
  • Task model
  • Interference
  • Multicore architectures

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