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Complexity of Scheduling in Synthesizing Hardware from Concurrent Action Oriented Specifications

Authors: Gaurav Singh, S. S. Ravi, Sumit Ahuja, and Sandeep Shukla

Published in: Dagstuhl Seminar Proceedings, Volume 7041, Power-aware Computing Systems (2007)

Abstract

Concurrent Action Oriented Specifications (CAOS) formalism such as Bluespec Inc.'s Bluespec System Verilog (BSV) has been recently shown to be effective for hardware modeling and synthesis. This formalism offers the benefits of automatic handling of concurrency issues in highly concurrent system descriptions, and the associated synthesis algorithms have been shown to produce efficient hardware comparable to those generated from hand-written Verilog/VHDL. These benefits which are inherent in such a synthesis process also aid in faster architectural exploration. This is because CAOS allows a high-level description (above RTL) of a design in terms of atomic transactions, where each transaction corresponds to a collection of operations. Optimal scheduling of such actions in CAOS-based synthesis process is crucial in order to generate hardware that is efficient in terms of area, latency and power. In this paper, we analyze the complexity of the scheduling problems associated with CAOS-based synthesis and discuss several heuristics for meeting the peak power goals of designs generated from CAOS. We also discuss approximability of these problems as appropriate.

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Gaurav Singh, S. S. Ravi, Sumit Ahuja, and Sandeep Shukla. Complexity of Scheduling in Synthesizing Hardware from Concurrent Action Oriented Specifications. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 7041, pp. 1-25, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2007)

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@InProceedings{singh_et_al:DagSemProc.07041.6,
  author =	{Singh, Gaurav and Ravi, S. S. and Ahuja, Sumit and Shukla, Sandeep},
  title =	{{Complexity of Scheduling in Synthesizing Hardware from Concurrent Action Oriented Specifications}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--25},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2007},
  volume =	{7041},
  editor =	{Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.07041.6},
  URN =		{urn:nbn:de:0030-drops-11055},
  doi =		{10.4230/DagSemProc.07041.6},
  annote =	{Keywords: Hardware Synthesis, Concurrent Action Oriented Specifications (CAOS), Scheduling, Complexity, Peak Power.}
}

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Complexity of Scheduling in Synthesizing Hardware from Concurrent Action Oriented Specifications

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