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Lessons Learned from last 4 Years of Reconfigurable Computing

Authors: Walter Stechele, Christopher Claus, and Andreas Laika

Published in: Dagstuhl Seminar Proceedings, Volume 10281, Dynamically Reconfigurable Architectures (2010)

Abstract

Partial dynamic reconfiguration of FPGAs was investigated for video-based driver assistance applications during the last 4 years. High-level application software was combined with dynamically reconfigurable hardware accelerators in selected scenarios, e.g. vehicle lights detection, optical flow motion detection. From the beginning of the project, various research challenges have been targeted, including hardware/software partitioning between embedded RISC and accelerators, granularity of reconfigurable regions, as well as the impact of the reconfiguration process on system performance. This article will review the status of these research challenges and present an outlook on future challenges, including reconfiguration look ahead. Challenges will be illustrated on robotic vision scenarios with dynamically changing computational load from soft real-time and hard real-time applications.

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Walter Stechele, Christopher Claus, and Andreas Laika. Lessons Learned from last 4 Years of Reconfigurable Computing. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 10281, pp. 1-7, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010)

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@InProceedings{stechele_et_al:DagSemProc.10281.8,
  author =	{Stechele, Walter and Claus, Christopher and Laika, Andreas},
  title =	{{Lessons Learned from last 4 Years of Reconfigurable Computing}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--7},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{10281},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.10281.8},
  URN =		{urn:nbn:de:0030-drops-28352},
  doi =		{10.4230/DagSemProc.10281.8},
  annote =	{Keywords: Reconfigurable computing, vision-based driver assistance}
}

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DOI: 10.4230/DagSemProc.06141.15

Reconfigurable Processing Units vs. Reconfigurable Interconnects

Authors: Andreas Herkersdorf, Christopher Claus, Michael Meitinger, Rainer Ohlendorf, and Thomas Wild

Published in: Dagstuhl Seminar Proceedings, Volume 6141, Dynamically Reconfigurable Architectures (2006)

Abstract

The question we proposed to explore with the seminar participants is whether the dynamic reconfigurable computing community is paying sufficient attention to the subject of dynamic reconfigurable SoC interconnects. By SoC interconnect, we refer to architecture- or system-level building blocks such as on-chip buses, crossbars, add-drop rings or meshed NoCs. P Our motivation to systematically investigate this question originates from conceptual and architectural challenges in the FlexPath project. FlexPath is a new Network Processor architecture that flexibly maps networking functions onto both SW programmable CPU resources and (re-)configurable HW building blocks in a way that different packet flows are forwarded via different, optimized processing paths. Packets with well defined processing requirements may even bypass the central CPU complex (AutoRoute). In consequence, CPU processing resources are more effectively used and the overall NP throughput is improved compared to conventional NPU architectures. P The following requirements apply with respect to the dynamic adaptation of the processing paths: The rule basis for NPU-internal processing path lookup is updated in the order of 100us, packet inter-arrival time is in the order of 100ns. Partial reconfiguration of the rule basis (and/or interconnect structure) with state of the art techniques would take several ms resulting in a continuously blocked system. However, performing path selection with conventional lookup table search and updates (and a statically configured on-chip bus) takes considerably less than 100ns. Hence, is there a need for new conceptual approaches with respect to dynamic SoC interconnect reconfiguration, or is this a ''no issue'' as conventional techniques are sufficient?

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Andreas Herkersdorf, Christopher Claus, Michael Meitinger, Rainer Ohlendorf, and Thomas Wild. Reconfigurable Processing Units vs. Reconfigurable Interconnects. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, pp. 1-3, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{herkersdorf_et_al:DagSemProc.06141.15,
  author =	{Herkersdorf, Andreas and Claus, Christopher and Meitinger, Michael and Ohlendorf, Rainer and Wild, Thomas},
  title =	{{Reconfigurable Processing Units vs. Reconfigurable Interconnects}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--3},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.15},
  URN =		{urn:nbn:de:0030-drops-7797},
  doi =		{10.4230/DagSemProc.06141.15},
  annote =	{Keywords: Reconfigurable SoC interconnect}
}

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Documents authored by Claus, Christopher

Lessons Learned from last 4 Years of Reconfigurable Computing

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Reconfigurable Processing Units vs. Reconfigurable Interconnects

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