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Requirements for and Design of a Processor with Predictable Timing

Authors: Christoph Berg, Jakob Engblom, and Reinhard Wilhelm

Published in: Dagstuhl Seminar Proceedings, Volume 3471, Perspectives Workshop: Design of Systems with Predictable Behaviour (2004)

Abstract

This paper introduces a set of design principles that aim to make processor architectures amenable to static timing analysis. Based on these principles, we give a design of a hard real-time processor with predictable timing, which is simultaneously capable of reaching respectable performance levels. The design principles we identify are recoverability from information loss in the analysis, minimal variation of the instruction timing, non-interference between processor components, deterministic processor behavior, and comprehensive documentation. The principles are based on our experience and that of other researchers in building timing analysis tools for existing processors.

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Christoph Berg, Jakob Engblom, and Reinhard Wilhelm. Requirements for and Design of a Processor with Predictable Timing. In Perspectives Workshop: Design of Systems with Predictable Behaviour. Dagstuhl Seminar Proceedings, Volume 3471, pp. 1-20, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2004)

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@InProceedings{berg_et_al:DagSemProc.03471.4,
  author =	{Berg, Christoph and Engblom, Jakob and Wilhelm, Reinhard},
  title =	{{Requirements for and Design of a Processor with Predictable Timing}},
  booktitle =	{Perspectives Workshop: Design of Systems with Predictable Behaviour},
  pages =	{1--20},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2004},
  volume =	{3471},
  editor =	{Lothar Thiele and Reinhard Wilhelm},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.03471.4},
  URN =		{urn:nbn:de:0030-drops-57},
  doi =		{10.4230/DagSemProc.03471.4},
  annote =	{Keywords: WCET, hard real-time, embedded systems, computer architecture}
}

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Requirements for and Design of a Processor with Predictable Timing

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