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Towards a reconfigurable hardware architecture for implementing a LDPC module suitable for software radio systems

Authors: Rene Cumplido, Juan Manuel Campos, Claudia Feregrino-Uribe, and Jose Roberto Perez-Andrade

Published in: Dagstuhl Seminar Proceedings, Volume 10281, Dynamically Reconfigurable Architectures (2010)

Abstract

Forward Error Correction is a key piece in modern digital communications. When a signal is transmitted over a noisy channel, multiple errors are generated. FEC techniques are directed towards the recovery of such errors. In last years, LDPC (Low Density Parity Check) codes have attracted attention of researchers because of their excellent error correction capabilities, but for actual radios high performance is not enough since they require to communicate with other multiple radios too. In general, communication between multiple radios requires the use of different standards. In this sense, Software Defined Radio (SDR) approach allows building multi standard radios based on reconfigurability abilities which means that base components including recovery errors block must provide reconfigurable options. In this paper, some open problems in designing and implementing reconfigurable LDPC components are presented and discussed. Some features of works in the state of the art are commented and possible research lines proposed.

Cite as

Rene Cumplido, Juan Manuel Campos, Claudia Feregrino-Uribe, and Jose Roberto Perez-Andrade. Towards a reconfigurable hardware architecture for implementing a LDPC module suitable for software radio systems. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 10281, pp. 1-8, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010)

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@InProceedings{cumplido_et_al:DagSemProc.10281.13,
  author =	{Cumplido, Rene and Campos, Juan Manuel and Feregrino-Uribe, Claudia and Perez-Andrade, Jose Roberto},
  title =	{{Towards a reconfigurable hardware architecture for implementing a LDPC module suitable for software radio systems}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--8},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{10281},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.10281.13},
  URN =		{urn:nbn:de:0030-drops-28950},
  doi =		{10.4230/DagSemProc.10281.13},
  annote =	{Keywords: LDPC codes, Software Defined Radio, Hardware Implementation}
}

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Towards a reconfigurable hardware architecture for implementing a LDPC module suitable for software radio systems

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