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Documents authored by Mitra, Tulika

Document
DOI: 10.4230/DagRep.6.10.120
Adaptive Isolation for Predictability and Security (Dagstuhl Seminar 16441)

Authors: Tulika Mitra, Jürgen Teich, and Lothar Thiele

Published in: Dagstuhl Reports, Volume 6, Issue 10 (2017)

Abstract
This report documents the program and the outcomes of Dagstuhl Seminar 16441 "Adaptive Isolation for Predictability and Security". Semiconductor technology is at the verge of integrating hundreds of processor cores on a single device. Indeed, affordable multi-processor system-on-a-chip (MPSoC) technology is becoming available. It is already heavily used for acceleration of applications from domains of graphics, gaming (e.g., GPUs) and high performance computing (e.g., Xeon Phi). The potential of MPSoCs is yet to explode for novel application areas of embedded and cyber-physical systems such as the domains of automotive (e.g., driver assistance systems), industrial automation and avionics where non-functional aspects of program execution must be enforceable. Instead of best-effort and average performance, these real-time applications demand timing predictability and/or security levels specifiable on a per-application basis. Therefore the cross-cutting topics of the seminar were methods for temporal and spatial isolation. These methods were discussed for their capabilities to enforce the above non-functional properties without sacrificing any efficiency or resource utilization. To be able to provide isolation instantaneously, e.g., even for just segments of a program under execution, adaptivity is essential at all hardware- and software layers. Support for adaptivity was the second focal aspect of the seminar. Here, virtualization and new adaptive resource reservation protocols were discussed and analyzed for their capabilities to provide application/job-wise predictable program execution qualities on demand at some costs and overheads. If the overhead can be kept low, there is a chance that adaptive isolation, the title of the seminar, may enable the adoption of MPSoC technology for many new application areas of embedded systems.
Cite as

Tulika Mitra, Jürgen Teich, and Lothar Thiele. Adaptive Isolation for Predictability and Security (Dagstuhl Seminar 16441). In Dagstuhl Reports, Volume 6, Issue 10, pp. 120-153, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)

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@Article{mitra_et_al:DagRep.6.10.120,
  author =	{Mitra, Tulika and Teich, J\"{u}rgen and Thiele, Lothar},
  title =	{{Adaptive Isolation for Predictability and Security (Dagstuhl Seminar 16441)}},
  pages =	{120--153},
  journal =	{Dagstuhl Reports},
  ISSN =	{2192-5283},
  year =	{2017},
  volume =	{6},
  number =	{10},
  editor =	{Mitra, Tulika and Teich, J\"{u}rgen and Thiele, Lothar},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagRep.6.10.120},
  URN =		{urn:nbn:de:0030-drops-69539},
  doi =		{10.4230/DagRep.6.10.120},
  annote =	{Keywords: Adaptive isolation, Embedded systems, Real-Time systems, Predictability, Security, MPSoC, Parallel computing, Programming models, Timing analysis, Virtualization}
}
Document
DOI: 10.4230/OASIcs.WCET.2007.1192
Timing Analysis of Body Area Network Applications

Authors: Liang Yun, Abhik Roychoudhury, and Tulika Mitra

Published in: OASIcs, Volume 6, 7th International Workshop on Worst-Case Execution Time Analysis (WCET'07) (2007)

Abstract
Body area network (BAN) applications have stringent timing requirements. The timing behavior of a BAN application is determined not only by the software complexity, inputs, and architecture, but also by the timing behavior of the peripherals. This paper presents systematic timing analysis of such applications, deployed for health-care monitoring of patients staying at home. This monitoring is used to achieve prompt notification of the hospital when a patient shows abnormal vital signs. Due to the safetycritical nature of these applications,worst-case execution time (WCET) analysis is extremely important.
Cite as

Liang Yun, Abhik Roychoudhury, and Tulika Mitra. Timing Analysis of Body Area Network Applications. In 7th International Workshop on Worst-Case Execution Time Analysis (WCET'07). Open Access Series in Informatics (OASIcs), Volume 6, pp. 1-6, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2007)

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@InProceedings{yun_et_al:OASIcs.WCET.2007.1192,
  author =	{Yun, Liang and Roychoudhury, Abhik and Mitra, Tulika},
  title =	{{Timing Analysis of Body Area Network Applications}},
  booktitle =	{7th International Workshop on Worst-Case Execution Time Analysis (WCET'07)},
  pages =	{1--6},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-05-7},
  ISSN =	{2190-6807},
  year =	{2007},
  volume =	{6},
  editor =	{Rochange, Christine},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2007.1192},
  URN =		{urn:nbn:de:0030-drops-11924},
  doi =		{10.4230/OASIcs.WCET.2007.1192},
  annote =	{Keywords: WCET analysis of Peripherals, Body Area Network applications}
}
Document
DOI: 10.4230/OASIcs.WCET.2005.816
Exploiting Branch Constraints without Exhaustive Path Enumeration

Authors: Ting Chen, Tulika Mitra, Abhik Roychoudhury, and Vivy Suhendra

Published in: OASIcs, Volume 1, 5th International Workshop on Worst-Case Execution Time Analysis (WCET'05) (2007)

Abstract
Statically estimating the worst case execution time (WCET) of a program is important for real-time software. This is difficult even in the programming language level due to the inherent difficulty in detecting and exploiting infeasible paths in a program’s control flow graph. In this paper, we propose an efficient method to exploit infeasible path information for WCET estimation of a loop without resorting to exhaustive path enumeration. The ef- ficiency of our approach is demonstrated with a real-life control-intensive program.
Cite as

Ting Chen, Tulika Mitra, Abhik Roychoudhury, and Vivy Suhendra. Exploiting Branch Constraints without Exhaustive Path Enumeration. In 5th International Workshop on Worst-Case Execution Time Analysis (WCET'05). Open Access Series in Informatics (OASIcs), Volume 1, pp. 46-49, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2007)

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@InProceedings{chen_et_al:OASIcs.WCET.2005.816,
  author =	{Chen, Ting and Mitra, Tulika and Roychoudhury, Abhik and Suhendra, Vivy},
  title =	{{Exploiting Branch Constraints without Exhaustive Path Enumeration}},
  booktitle =	{5th International Workshop on Worst-Case Execution Time Analysis (WCET'05)},
  pages =	{46--49},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-24-8},
  ISSN =	{2190-6807},
  year =	{2007},
  volume =	{1},
  editor =	{Wilhelm, Reinhard},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2005.816},
  URN =		{urn:nbn:de:0030-drops-8163},
  doi =		{10.4230/OASIcs.WCET.2005.816},
  annote =	{Keywords: WCET, infeasible path, branch constraints}
}
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