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Documents authored by Polian, Ilia

Document
DOI: 10.4230/DagRep.9.7.94
Secure Composition for Hardware Systems (Dagstuhl Seminar 19301)

Authors: Divya Arora, Ilia Polian, Francesco Regazzoni, and Patrick Schaumont

Published in: Dagstuhl Reports, Volume 9, Issue 7 (2020)

Abstract
The goal of the Dagstuhl Seminar 19301 ``Secure Composition for Hardware System'' was to establish a common understanding of principles and techniques that can facilitate composition and integration of hardware systems to achieve specified security guarantees. Theoretical foundations of secure composition have been laid out in the past, but they are limited to software systems. New and unique security challenges arise when a real system composed of a range of hardware components, including application-specific blocks, programmable microcontrollers, and reconfigurable fabrics, are put together. For example, these components may have different owners, different trust assumptions and may not even have a common language to describe their security properties to each other. Physical and side-channel attacks that take advantage of various physical properties to undermine a system's security objectives add another level of complexity to the secure composition problem. Moreover, practical hardware systems include software of tremendous size and complexity, and hardware-software interaction can create new security challenges. The seminar considered secure composition both from a pure hardware perspective, where multiple hardware blocks are composed in, e.g., a system on chip (SoC), and from a hardware-software perspective where hardware is integrated within a system that includes software. The seminar brought together researchers and industry practitioners from fields that have to deal with secure composition: Secure hardware architectures, hardware-oriented security, applied cryptography, test and verification of security properties. By involving industrial participants, we were able to get insights on real-world challenges, heuristics, and methodologies employed to address them and initiate a discussion towards new solutions.
Cite as

Divya Arora, Ilia Polian, Francesco Regazzoni, and Patrick Schaumont. Secure Composition for Hardware Systems (Dagstuhl Seminar 19301). In Dagstuhl Reports, Volume 9, Issue 7, pp. 94-116, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)

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@Article{arora_et_al:DagRep.9.7.94,
  author =	{Arora, Divya and Polian, Ilia and Regazzoni, Francesco and Schaumont, Patrick},
  title =	{{Secure Composition for Hardware Systems (Dagstuhl Seminar 19301)}},
  pages =	{94--116},
  journal =	{Dagstuhl Reports},
  ISSN =	{2192-5283},
  year =	{2019},
  volume =	{9},
  number =	{7},
  editor =	{Arora, Divya and Polian, Ilia and Regazzoni, Francesco and Schaumont, Patrick},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagRep.9.7.94},
  URN =		{urn:nbn:de:0030-drops-116377},
  doi =		{10.4230/DagRep.9.7.94},
  annote =	{Keywords: Hardware, Secure composition, Security, Software}
}
Document
DOI: 10.4230/DagRep.6.5.72
Hardware Security (Dagstuhl Seminar 16202)

Authors: Osnat Keren, Ilia Polian, and Mark M. Tehranipoor

Published in: Dagstuhl Reports, Volume 6, Issue 5 (2016)

Abstract
This report documents the program and outcomes of Dagstuhl Seminar 16202 ``Hardware Security", which was held in Schloss Dagstuhl- Leibniz Center for Informatics from May 16- 20, 2016. This seminar aims to bring together a group of researchers, who are actively involved in the design and the security assessment of hardware primitives. The seminar was organized around presentations given by several participants on their current research, and ongoing work. In addition to these presentations, the program also included three discussion sessions, and two special sessions on curriculum development and funding programs. The seminar was indeed successful in familiarizing the researchers with recent developments in hardware security field of study, providing better understanding of still unsolved problems, and pointing out future research directions. The paper is further organized as follows. Section 1 summarizes the most important goals of the seminar. Section is devoted to the abstracts of the presentations given in the seminar, whereas in Section 4 the abstracts of the discussion sessions are provided.
Cite as

Osnat Keren, Ilia Polian, and Mark M. Tehranipoor. Hardware Security (Dagstuhl Seminar 16202). In Dagstuhl Reports, Volume 6, Issue 5, pp. 72-93, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)

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@Article{keren_et_al:DagRep.6.5.72,
  author =	{Keren, Osnat and Polian, Ilia and Tehranipoor, Mark M.},
  title =	{{Hardware Security (Dagstuhl Seminar 16202)}},
  pages =	{72--93},
  journal =	{Dagstuhl Reports},
  ISSN =	{2192-5283},
  year =	{2016},
  volume =	{6},
  number =	{5},
  editor =	{Keren, Osnat and Polian, Ilia and Tehranipoor, Mark M.},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagRep.6.5.72},
  URN =		{urn:nbn:de:0030-drops-67218},
  doi =		{10.4230/DagRep.6.5.72},
  annote =	{Keywords: Hardware security; Passive and active side-channel analysis; Machine learning; Cryptographic blocks; True random number generators; Physically unclonable functions; Hardware Trojan}
}
Document
DOI: 10.4230/OASIcs.WCET.2006.671
A Definition and Classification of Timing Anomalies

Authors: Jan Reineke, Björn Wachter, Stefan Thesing, Reinhard Wilhelm, Ilia Polian, Jochen Eisinger, and Bernd Becker

Published in: OASIcs, Volume 4, 6th International Workshop on Worst-Case Execution Time Analysis (WCET'06) (2006)

Abstract
Timing Anomalies are characterized by counterintuitive timing behaviour. A locally faster execution leads to an increase of the execution time of the whole program. The presence of such behaviour makes WCET analysis more difficult: It is not safe to assume local worst-case behaviour wherever the analysis encounters uncertainty. Existing definitions of Timing Anomalies are rather imprecise and intuitive in nature. Some do not cover all kinds of known Timing Anomalies. After giving an overview of related work, we give a concise formal definition of Timing Anomalies. We then begin to identify different classes of anomalies. One of these classes, coined Scheduling Timing Anomalies, coincides with previous restricted definitions.
Cite as

Jan Reineke, Björn Wachter, Stefan Thesing, Reinhard Wilhelm, Ilia Polian, Jochen Eisinger, and Bernd Becker. A Definition and Classification of Timing Anomalies. In 6th International Workshop on Worst-Case Execution Time Analysis (WCET'06). Open Access Series in Informatics (OASIcs), Volume 4, pp. 1-6, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{reineke_et_al:OASIcs.WCET.2006.671,
  author =	{Reineke, Jan and Wachter, Bj\"{o}rn and Thesing, Stefan and Wilhelm, Reinhard and Polian, Ilia and Eisinger, Jochen and Becker, Bernd},
  title =	{{A Definition and Classification of Timing Anomalies}},
  booktitle =	{6th International Workshop on Worst-Case Execution Time Analysis (WCET'06)},
  pages =	{1--6},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-03-3},
  ISSN =	{2190-6807},
  year =	{2006},
  volume =	{4},
  editor =	{Mueller, Frank},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2006.671},
  URN =		{urn:nbn:de:0030-drops-6713},
  doi =		{10.4230/OASIcs.WCET.2006.671},
  annote =	{Keywords: Timing analysis, Worst-case execution time, Timing anomalies, Scheduling Anomalies, Abstraction}
}
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