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Implementation of Memory Centric Scheduling for COTS Multi-Core Real-Time Systems

Authors Juan M. Rivas, Joël Goossens, Xavier Poczekajlo, Antonio Paolillo

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Author Details

Juan M. Rivas
  • PARTS Research Centre, Université libre de Bruxelles, Brussels, Belgium
Joël Goossens
  • PARTS Research Centre, Université libre de Bruxelles, Brussels, Belgium
Xavier Poczekajlo
  • PARTS Research Centre, Université libre de Bruxelles, Brussels, Belgium
Antonio Paolillo
  • HIPPEROS S.A., Louvain-la-Neuve, Belgium

Funding

  • Rivas, Juan M.: This research was funded by Wallonia Region (Belgium) BEWARE grant PARTITA (1610375).

Cite AsGet BibTex

Juan M. Rivas, Joël Goossens, Xavier Poczekajlo, and Antonio Paolillo. Implementation of Memory Centric Scheduling for COTS Multi-Core Real-Time Systems. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 7:1-7:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
https://doi.org/10.4230/LIPIcs.ECRTS.2019.7

Abstract

The demands for high performance computing with a low cost and low power consumption are driving a transition towards multi-core processors in many consumer and industrial applications. However, the adoption of multi-core processors in the domain of real-time systems faces a series of challenges that has been the focus of great research intensity during the last decade. These challenges arise in great part from the non real-time nature of the hardware arbiters that schedule the access to shared resources, such as the main memory. One solution proposed in the literature is called Memory Centric Scheduling, which defines a separate software scheduler for the sections of the tasks that will access the main memory, hence circumventing the low level unpredictable hardware arbiters. Several Memory Centric schedulers and associated theoretical analyses have been proposed, but as far as we know, no actual implementation of the required OS-level underpinnings to support dynamic event-driven Memory Centric Scheduling has been presented before. In this paper we aim to fill this gap, targeting cache based COTS multi-core systems. We will confirm via measurements the main theoretical benefits of Memory Centric Scheduling (e.g. task isolation). Furthermore, we will describe an effective schedulability analysis using concepts from distributed systems.

Subject Classification

ACM Subject Classification
  • Computer systems organization → Real-time systems
Keywords
  • real-time
  • multi-core
  • memory centric
  • predictability
  • implementation
  • rtos

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