Understanding Shared Memory Bank Access Interference in Multi-Core Avionics

Authors Andreas Löfwenmark, Simin Nadjm-Tehrani



PDF
Thumbnail PDF

File

OASIcs.WCET.2016.12.pdf
  • Filesize: 426 kB
  • 11 pages

Document Identifiers

Author Details

Andreas Löfwenmark
Simin Nadjm-Tehrani

Cite AsGet BibTex

Andreas Löfwenmark and Simin Nadjm-Tehrani. Understanding Shared Memory Bank Access Interference in Multi-Core Avionics. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016). Open Access Series in Informatics (OASIcs), Volume 55, pp. 12:1-12:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)
https://doi.org/10.4230/OASIcs.WCET.2016.12

Abstract

Deployment of multi-core platforms in safety-critical applications requires reliable estimation of worst-case response time (WCRT) for critical processes. Determination of WCRT needs to accurately estimate and measure the interferences arising from multiple processes and multiple cores. Earlier works have proposed frameworks in which CPU, shared cache, and shared memory (DRAM) interferences can be estimated using some application and platform-dependent parameters. In this work we examine a recent work in which single core equivalent (SCE) worst case execution time is used as a basis for deriving WCRT. We describe the specific requirements in an avionics context including the sharing of memory banks by multiple processes on multiple cores, and adapt the SCE framework to account for them. We present the needed adaptations to a real-time operating system to enforce the requirements, and present a methodology for validating the theoretical WCRT through measurements on the resulting platform. The work reveals that the framework indeed creates a (pessimistic) bound on the WCRT. It also discloses that the maximum interference for memory accesses does not arise when all cores share the same memory bank.
Keywords
  • multi-core
  • avionics
  • shared memory systems
  • WCET

Metrics

  • Access Statistics
  • Total Accesses (updated on a weekly basis)
    0
    PDF Downloads

References

  1. Aeronautical Radio Inc (ARINC). ARINC 653: Avionics application software standard interface part 1 - required services, 2010. Google Scholar
  2. James H. Anderson, Sanjoy K. Baruah, and Björn B. Brandenburg. Multicore operating-system support for mixed criticality. In Proc. of Workshop on Mixed Criticality: Roadmap to Evolving UAV Certification, 2009. Google Scholar
  3. Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, and Francisco J. Cazorla. Resource usage templates and signatures for cots multicore processors. In Proc. of 52nd Annual Design Automation Conference, DAC'15, pages 155:1-155:6, New York, NY, USA, 2015. ACM. URL: http://dx.doi.org/10.1145/2744769.2744901.
  4. J. L. Herman, C. J. Kenna, M. S. Mollison, J. H. Anderson, and D. M. Johnson. RTOS support for multicore mixed-criticality systems. In Proc. of 18th IEEE Real-Time and Embedded Technology and Applications Symposium, pages 197-208, 2012. URL: http://dx.doi.org/10.1109/RTAS.2012.24.
  5. R. Inam, N. Mahmud, M. Behnam, T. Nolte, and M. Sjödin. The multi-resource server for predictable execution on multi-core platforms. In Proc. of 20th IEEE Real-Time and Embedded Technology and Applications Symposium, 2014. Google Scholar
  6. Joint Electron Device Engineering Council (JEDEC). DDR3 SDRAM Standard, 2012. URL: http://www.jedec.org/standards-documents/docs/jesd-79-3d.
  7. M. Joseph and P. Pandya. Finding response times in a real-time system. The Computer Journal, 29(5):390-395, 1986. URL: http://comjnl.oxfordjournals.org/content/29/5/390.abstract, http://arxiv.org/abs/http://comjnl.oxfordjournals.org/content/29/5/390.full.pdf+html, URL: http://dx.doi.org/10.1093/comjnl/29.5.390.
  8. H. Kim, D. de Niz, B. Andersson, M. Klein, O. Mutlu, and R. Rajkumar. Bounding memory interference delay in cots-based multi-core systems. In Proc. of 20th IEEE Real-Time and Embedded Technology and Applications Symposium, pages 145-154, 2014. URL: http://dx.doi.org/10.1109/RTAS.2014.6925998.
  9. A. Löfwenmark and S. Nadjm-Tehrani. Challenges in future avionic systems on multi-core platforms. In Proc. of 25th IEEE International Symposium on Software Reliability Engineering Workshops, pages 115-119, 2014. URL: http://dx.doi.org/10.1109/ISSREW.2014.70.
  10. A. Löfwenmark and S. Nadjm-Tehrani. Experience report: Memory accesses for avionic applications and operating systems on a multi-core platform. In Proc. of 26th IEEE International Symposium on Software Reliability Engineering, pages 153-160, 2015. URL: http://dx.doi.org/10.1109/ISSRE.2015.7381809.
  11. R. Mancuso, R. Dudko, E. Betti, M. Cesati, M. Caccamo, and R. Pellizzoni. Real-time cache management framework for multi-core architectures. In Proc. of 19th IEEE Real-Time and Embedded Technology and Applications Symposium, pages 45-54, 2013. URL: http://dx.doi.org/10.1109/RTAS.2013.6531078.
  12. R. Mancuso, R. Pellizzoni, M. Caccamo, Lui Sha, and Heechul Yun. WCET(m) estimation in multi-core systems using single core equivalence. In Proc. of 27th Euromicro Conference on Real-Time Systems, pages 174-183, 2015. URL: http://dx.doi.org/10.1109/ECRTS.2015.23.
  13. M. S. Mollison, J. P. Erickson, J. H. Anderson, S. K. Baruah, and J. A. Scoredos. Mixed-criticality real-time scheduling for multicore systems. In Proc. of 10th International Conference on Computer and Information Technology, pages 1864-1871, 2010. URL: http://dx.doi.org/10.1109/CIT.2010.320.
  14. J. Nowotsch, M. Paulitsch, D. Buhler, H. Theiling, S. Wegener, and M. Schmidt. Multi-core interference-sensitive WCET analysis leveraging runtime resource capacity enforcement. In Proc. of 26th Euromicro Conference on Real-Time Systems, pages 109-118, 2014. URL: http://dx.doi.org/10.1109/ECRTS.2014.20.
  15. M. Paolieri, E. Quiñones, F. J. Cazorla, and M. Valero. An analyzable memory controller for hard real-time cmps. IEEE Embedded Systems Letters, 1(4):86-90, 2009. URL: http://dx.doi.org/10.1109/LES.2010.2041634.
  16. Jan Reineke, Isaac Liu, Hiren D. Patel, Sungjun Kim, and Edward A. Lee. Pret dram controller: Bank privatization for predictability and temporal isolation. In Proc. of the 7th International Conference on Hardware/Software Codesign and System Synthesis, pages 99-108, 2011. URL: http://dx.doi.org/10.1145/2039370.2039388.
  17. RTCA, Inc. RTCA/DO-297, integrated modular avionics (IMA) development, guidance and certification considerations, 2005. Google Scholar
  18. RTCA, Inc. RTCA/DO-178C, software considerations in airborne systems and equipment certification, 2012. Google Scholar
  19. B. C. Ward, J. L. Herman, C. J. Kenna, and J. H. Anderson. Making shared caches more predictable on multicore platforms. In Proc. of 25th Euromicro Conference on Real-Time Systems, pages 157-167, 2013. URL: http://dx.doi.org/10.1109/ECRTS.2013.26.
  20. Jack Whitham, Neil C. Audsley, and Robert I. Davis. Explicit reservation of cache memory in a predictable, preemptive multitasking real-time system. ACM Trans. Embed. Comput. Syst., 13(4s):120:1-120:25, April 2014. URL: http://dx.doi.org/10.1145/2523070.
  21. Zheng Pei Wu, Y. Krish, and R. Pellizzoni. Worst case analysis of dram latency in multi-requestor systems. In Proc. of 34th Real-Time Systems Symposium, pages 372-383, 2013. URL: http://dx.doi.org/10.1109/RTSS.2013.44.
  22. H. Yun, R. Pellizzon, and P. K. Valsan. Parallelism-aware memory interference delay analysis for cots multicore systems. In Proc. of 27th Euromicro Conference on Real-Time Systems, pages 184-195, 2015. URL: http://dx.doi.org/10.1109/ECRTS.2015.24.
  23. Heechul Yun, R. Mancuso, Zheng-Pei Wu, and R. Pellizzoni. Palloc: Dram bank-aware memory allocator for performance isolation on multicore platforms. In Proc. of 20th IEEE Real-Time and Embedded Technology and Applications Symposium, pages 155-166, 2014. URL: http://dx.doi.org/10.1109/RTAS.2014.6925999.
  24. Heechul Yun, Gang Yao, R. Pellizzoni, M. Caccamo, and Lui Sha. Memguard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms. In Proc. of 19th IEEE Real-Time and Embedded Technology and Applications Symposium, pages 55-64, 2013. URL: http://dx.doi.org/10.1109/RTAS.2013.6531079.
Questions / Remarks / Feedback
X

Feedback for Dagstuhl Publishing


Thanks for your feedback!

Feedback submitted

Could not send message

Please try again later or send an E-mail