Volume
OASIcs, Volume 55
16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)
-
Part of:
Series:
Open Access Series in Informatics (OASIcs)
Conference: Workshop on Worst-Case Execution Time Analysis (WCET)
Event
WCET 2016, July 5, 2016, Toulouse, FranceEditor
Publication Details
- published at: 2016-12-20
- Publisher: Schloss Dagstuhl – Leibniz-Zentrum für Informatik
- ISBN: 978-3-95977-025-5
- DBLP: db/conf/wcet/wcet2016
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Document
Complete Volume
OASIcs, Volume 55, WCET'16, Complete Volume
Abstract
OASIcs, Volume 55, WCET'16, Complete Volume
Cite as
16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016). Open Access Series in Informatics (OASIcs), Volume 55, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)
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@Proceedings{schoeberl:OASIcs.WCET.2016,
title = {{OASIcs, Volume 55, WCET'16, Complete Volume}},
booktitle = {16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-025-5},
ISSN = {2190-6807},
year = {2016},
volume = {55},
editor = {Schoeberl, Martin},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016},
URN = {urn:nbn:de:0030-drops-69095},
doi = {10.4230/OASIcs.WCET.2016},
annote = {Keywords: Performance Analysis and Design Aids, Real-Time and Embedded systems, Software/- Program Verification, \lbrackOrganization and Design\rbrack Real-time Systems and Embedded Systems}
}
Document
Front Matter
Front Matter, Table of Contents, Preface, List of Authors, Committee
Abstract
Front Matter, Table of Contents, Preface, List of Authors, Committee
Cite as
16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016). Open Access Series in Informatics (OASIcs), Volume 55, pp. 0:i-0:xii, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)
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@InProceedings{schoeberl:OASIcs.WCET.2016.0,
author = {Schoeberl, Martin},
title = {{Front Matter, Table of Contents, Preface, List of Authors, Committee}},
booktitle = {16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
pages = {0:i--0:xii},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-025-5},
ISSN = {2190-6807},
year = {2016},
volume = {55},
editor = {Schoeberl, Martin},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.0},
URN = {urn:nbn:de:0030-drops-68939},
doi = {10.4230/OASIcs.WCET.2016.0},
annote = {Keywords: Front Matter, Table of Contents, Preface, List of Authors, Committee}
}
Document
Mitigating Software-Instrumentation Cache Effects in Measurement-Based Timing Analysis
Abstract
Measurement-based timing analysis (MBTA) is often used to determine the timing behaviour of software programs embedded in safety-aware real-time systems deployed in various industrial domains including automotive and railway. MBTA methods rely on some form of instrumentation, either at hardware or software level, of the target program or fragments thereof to collect execution-time measurement data. A known drawback of software-level instrumentation is that instrumentation itself does affect the timing and functional behaviour of a program, resulting in the so-called probe effect: leaving the instrumentation code in the final executable can negatively affect average performance and could not be even admissible under stringent industrial qualification and certification standards; removing it before operation jeopardizes the results of timing analysis as the WCET estimates on the instrumented version of the program cannot be valid any more due, for example, to the timing effects incurred by different cache alignments. In this paper, we present a novel approach to mitigate the impact of instrumentation code on cache behaviour by reducing the instrumentation overhead while at the same time preserving and consolidating the results of timing analysis.
Cite as
Enrique Díaz, Jaume Abella, Enrico Mezzetti, Irune Agirre, Mikel Azkarate-Askasua, Tullio Vardanega, and Francisco J. Cazorla. Mitigating Software-Instrumentation Cache Effects in Measurement-Based Timing Analysis. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016). Open Access Series in Informatics (OASIcs), Volume 55, pp. 1:1-1:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)
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@InProceedings{diaz_et_al:OASIcs.WCET.2016.1,
author = {D{\'\i}az, Enrique and Abella, Jaume and Mezzetti, Enrico and Agirre, Irune and Azkarate-Askasua, Mikel and Vardanega, Tullio and Cazorla, Francisco J.},
title = {{Mitigating Software-Instrumentation Cache Effects in Measurement-Based Timing Analysis}},
booktitle = {16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
pages = {1:1--1:11},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-025-5},
ISSN = {2190-6807},
year = {2016},
volume = {55},
editor = {Schoeberl, Martin},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.1},
URN = {urn:nbn:de:0030-drops-68946},
doi = {10.4230/OASIcs.WCET.2016.1},
annote = {Keywords: WCET, Measurements, Instrumentation overhead}
}
Document
TACLeBench: A Benchmark Collection to Support Worst-Case Execution Time Research
Abstract
Engineering related research, such as research on worst-case execution time, uses experimentation to evaluate ideas. For these experiments we need example programs. Furthermore, to make the research experimentation repeatable those programs shall be made publicly available.
We collected open-source programs, adapted them to a common coding style, and provide the collection in open-source. The benchmark collection is called TACLeBench and is available from GitHub in version 1.9 at the publication date of this paper. One of the main features of TACLeBench is that all programs are self-contained without any dependencies on standard libraries or an operating system.
Cite as
Heiko Falk, Sebastian Altmeyer, Peter Hellinckx, Björn Lisper, Wolfgang Puffitsch, Christine Rochange, Martin Schoeberl, Rasmus Bo Sørensen, Peter Wägemann, and Simon Wegener. TACLeBench: A Benchmark Collection to Support Worst-Case Execution Time Research. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016). Open Access Series in Informatics (OASIcs), Volume 55, pp. 2:1-2:10, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)
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@InProceedings{falk_et_al:OASIcs.WCET.2016.2,
author = {Falk, Heiko and Altmeyer, Sebastian and Hellinckx, Peter and Lisper, Bj\"{o}rn and Puffitsch, Wolfgang and Rochange, Christine and Schoeberl, Martin and S{\o}rensen, Rasmus Bo and W\"{a}gemann, Peter and Wegener, Simon},
title = {{TACLeBench: A Benchmark Collection to Support Worst-Case Execution Time Research}},
booktitle = {16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
pages = {2:1--2:10},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-025-5},
ISSN = {2190-6807},
year = {2016},
volume = {55},
editor = {Schoeberl, Martin},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.2},
URN = {urn:nbn:de:0030-drops-68958},
doi = {10.4230/OASIcs.WCET.2016.2},
annote = {Keywords: Benchmark, WCET analysis, real-time systems}
}
Document
Expressing and Exploiting Conflicts over Paths in WCET Analysis
Abstract
The presence of infeasible paths in a program is a source of imprecision in the Worst-Case Execution Time (WCET) analysis. Detecting, expressing and exploiting such paths can improve the WCET estimation or, at least, improve the confidence we have in estimation precision. In this article, we propose an extension of the FFX format to express conflicts over paths and we detail two ways of enhancing the WCET analyses with that information. We demonstrate and compare these techniques on the Mälardalen benchmark suite and on C code generated from Esterel.
Cite as
Vincent Mussot, Jordy Ruiz, Pascal Sotin, Marianne de Michiel, and Hugues Cassé. Expressing and Exploiting Conflicts over Paths in WCET Analysis. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016). Open Access Series in Informatics (OASIcs), Volume 55, pp. 3:1-3:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)
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@InProceedings{mussot_et_al:OASIcs.WCET.2016.3,
author = {Mussot, Vincent and Ruiz, Jordy and Sotin, Pascal and de Michiel, Marianne and Cass\'{e}, Hugues},
title = {{Expressing and Exploiting Conflicts over Paths in WCET Analysis}},
booktitle = {16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
pages = {3:1--3:11},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-025-5},
ISSN = {2190-6807},
year = {2016},
volume = {55},
editor = {Schoeberl, Martin},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.3},
URN = {urn:nbn:de:0030-drops-68966},
doi = {10.4230/OASIcs.WCET.2016.3},
annote = {Keywords: WCET analysis, Infeasible paths, Path conflicts, IPET, CFG transformation}
}
Document
Continuous Non-Intrusive Hybrid WCET Estimation Using Waypoint Graphs
Abstract
Traditionally, the Worst-Case Execution Time (WCET) of Embedded Software has been estimated using analytical approaches. This is effective, if good models of the processor/System-on-Chip (SoC) architecture exist. Unfortunately, modern high performance SoCs often contain unpredictable and/or undocumented components that influence the timing behaviour. Thus, analytical results for such processors are unrealistically pessimistic. One possible alternative approach seems to be hybrid WCET analysis, where measurement data together with an analytical approach is used to estimate worst-case behaviour. Previously, we demonstrated how continuous evaluation of basic block trace data can be used to produce detailed statistics of basic blocks in embedded software. In the meantime it has become clear that the trace data provided by modern SoCs delivers a different type of information. In this contribution, we show that even under realistic conditions, a meaningful analysis can be conducted with the trace data.
Cite as
Boris Dreyer, Christian Hochberger, Alexander Lange, Simon Wegener, and Alexander Weiss. Continuous Non-Intrusive Hybrid WCET Estimation Using Waypoint Graphs. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016). Open Access Series in Informatics (OASIcs), Volume 55, pp. 4:1-4:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)
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@InProceedings{dreyer_et_al:OASIcs.WCET.2016.4,
author = {Dreyer, Boris and Hochberger, Christian and Lange, Alexander and Wegener, Simon and Weiss, Alexander},
title = {{Continuous Non-Intrusive Hybrid WCET Estimation Using Waypoint Graphs}},
booktitle = {16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
pages = {4:1--4:11},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-025-5},
ISSN = {2190-6807},
year = {2016},
volume = {55},
editor = {Schoeberl, Martin},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.4},
URN = {urn:nbn:de:0030-drops-68977},
doi = {10.4230/OASIcs.WCET.2016.4},
annote = {Keywords: Hybrid Worst-Case Execution Time (WCET) Estimation for Multicore Processors, Real-time Systems}
}
Document
Eager Stack Cache Memory Transfers
Abstract
The growing complexity of modern computer architectures increasingly complicates the prediction of the run-time behavior of software. For real-time systems, where a safe estimation of the program's worst-case execution time is needed, time-predictable computer architectures promise to resolve this problem. The stack cache, for instance, allows the compiler to efficiently cache a program's stack, while static analysis of its behavior remains easy.
This work introduces an optimization of the stack cache that allows to anticipate memory transfers that might be initiated by future stack cache control instructions. These eager memory transfers thus allow to reduce the average-case latency of those control instructions, very similar to "prefetching" techniques known from conventional caches. However, the mechanism proposed here is guaranteed to have no impact on the worst-case execution time estimates computed by static analysis. Measurements on a dual-core platform using the Patmos processor and imedivision-multiplexing-based memory arbitration, show that our technique can eliminate up to 62% (7%) of the memory transfers from (respectively to) the stack cache on average over all programs of the MiBench benchmark suite.
Cite as
Amine Naji and Florian Brandner. Eager Stack Cache Memory Transfers. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016). Open Access Series in Informatics (OASIcs), Volume 55, pp. 5:1-5:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)
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@InProceedings{naji_et_al:OASIcs.WCET.2016.5,
author = {Naji, Amine and Brandner, Florian},
title = {{Eager Stack Cache Memory Transfers}},
booktitle = {16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
pages = {5:1--5:11},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-025-5},
ISSN = {2190-6807},
year = {2016},
volume = {55},
editor = {Schoeberl, Martin},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.5},
URN = {urn:nbn:de:0030-drops-68983},
doi = {10.4230/OASIcs.WCET.2016.5},
annote = {Keywords: Predictability, Eager Memory Transfers, Stack Cache, Real-Time Systems, Prefetching, Eager Eviction}
}
Document
The Variability of Application Execution Times on a Multi-Core Platform
Abstract
It is a known fact that processes running concurrently on different cores in a multicore environment interfere with each other on the processor shared resources. The contention on these shared resources considerably slows down the execution on every core since sometimes the cores must stall while their requests to access the resources are being served. But by how much the execution may be slowed down due to this interference? In this paper we answer this question with numbers coming from experimentation. That is, we quantify the magnitude of the impact of the interference on the execution time by running programs taken from the TACLeBench benchmark suite, a popular benchmark suite in the real-time research community, on the first generation of Kalray manycore processor family, the MPPA-256 (the development board) that goes by the codename "Andey".
Cite as
Vincent Nélis, Patrick Meumeu Yomsi, and Luís Miguel Pinho. The Variability of Application Execution Times on a Multi-Core Platform. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016). Open Access Series in Informatics (OASIcs), Volume 55, pp. 6:1-6:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)
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@InProceedings{nelis_et_al:OASIcs.WCET.2016.6,
author = {N\'{e}lis, Vincent and Yomsi, Patrick Meumeu and Pinho, Lu{\'\i}s Miguel},
title = {{The Variability of Application Execution Times on a Multi-Core Platform}},
booktitle = {16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
pages = {6:1--6:11},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-025-5},
ISSN = {2190-6807},
year = {2016},
volume = {55},
editor = {Schoeberl, Martin},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.6},
URN = {urn:nbn:de:0030-drops-68994},
doi = {10.4230/OASIcs.WCET.2016.6},
annote = {Keywords: Execution time variability, timing analysis, WCET estimates, multi-cores, many-cores}
}
Document
BEST: a Binary Executable Slicing Tool
Abstract
We describe the implementation of BEST, a tool for slicing binary code. We aim to integrate this tool in a WCET estimation framework based on model checking. In this approach, program slicing is used to abstract the program model in order to reduce the state space of the system. In this article, we also report on the results of an evaluation of the efficiency of the abstraction technique.
Cite as
Armel Mangean, Jean-Luc Béchennec, Mikaël Briday, and Sébastien Faucou. BEST: a Binary Executable Slicing Tool. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016). Open Access Series in Informatics (OASIcs), Volume 55, pp. 7:1-7:10, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)
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@InProceedings{mangean_et_al:OASIcs.WCET.2016.7,
author = {Mangean, Armel and B\'{e}chennec, Jean-Luc and Briday, Mika\"{e}l and Faucou, S\'{e}bastien},
title = {{BEST: a Binary Executable Slicing Tool}},
booktitle = {16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
pages = {7:1--7:10},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-025-5},
ISSN = {2190-6807},
year = {2016},
volume = {55},
editor = {Schoeberl, Martin},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.7},
URN = {urn:nbn:de:0030-drops-69004},
doi = {10.4230/OASIcs.WCET.2016.7},
annote = {Keywords: Program Slicing, Binary Code Analysis, WCET Analysis}
}
Document
Dynamic Branch Resolution Based on Combined Static Analyses
Abstract
Static analysis requires the full knowledge of the overall program structure. The structure of a program can be represented by a Control Flow Graph (CFG) where vertices are basic blocks (BB) and edges represent the control flow between the BB. To construct a full CFG, all the BB as well as all of their possible targets addresses must be found. In this paper, we present a method to resolve dynamic branches, that identifies the target addresses of BB created due to the switch-cases and calls on function pointers. We also implemented a slicing method to speed up the overall analysis which makes our approach applicable on large and realistic real-time programs.
Cite as
Wei-Tsun Sun and Hugues Cassé. Dynamic Branch Resolution Based on Combined Static Analyses. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016). Open Access Series in Informatics (OASIcs), Volume 55, pp. 8:1-8:10, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)
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@InProceedings{sun_et_al:OASIcs.WCET.2016.8,
author = {Sun, Wei-Tsun and Cass\'{e}, Hugues},
title = {{Dynamic Branch Resolution Based on Combined Static Analyses}},
booktitle = {16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
pages = {8:1--8:10},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-025-5},
ISSN = {2190-6807},
year = {2016},
volume = {55},
editor = {Schoeberl, Martin},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.8},
URN = {urn:nbn:de:0030-drops-69014},
doi = {10.4230/OASIcs.WCET.2016.8},
annote = {Keywords: WCET, static analysis, dynamic branch, assembly, machine language}
}
Document
Measurement-Based Timing Analysis of the AURIX Caches
Abstract
Cache memories are one of the hardware resources with higher potential to reduce worst-case execution time (WCET) costs for software programs with tight real-time constraints. Yet, the complexity of cache analysis has caused a large fraction of real-time systems industry to avoid using them, especially in the automotive sector. For measurement-based timing analysis (MBTA) - the dominant technique in domains such as automotive - cache challenges the definition of test scenarios stressful enough to produce (cache) layouts that causing high contention.
In this paper, we present our experience in enabling the use of caches for a real automotive application running on an AURIX multiprocessor, using software randomization and measurement-based probabilistic timing analysis (MBPTA). Our results show that software randomization successfully exposes - in the experiments performed for timing analysis - cache related variability, in a manner that can be effectively captured by MBPTA.
Cite as
Leonidas Kosmidis, Davide Compagnin, David Morales, Enrico Mezzetti, Eduardo Quinones, Jaume Abella, Tullio Vardanega, and Francisco J. Cazorla. Measurement-Based Timing Analysis of the AURIX Caches. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016). Open Access Series in Informatics (OASIcs), Volume 55, pp. 9:1-9:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)
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@InProceedings{kosmidis_et_al:OASIcs.WCET.2016.9,
author = {Kosmidis, Leonidas and Compagnin, Davide and Morales, David and Mezzetti, Enrico and Quinones, Eduardo and Abella, Jaume and Vardanega, Tullio and Cazorla, Francisco J.},
title = {{Measurement-Based Timing Analysis of the AURIX Caches}},
booktitle = {16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
pages = {9:1--9:11},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-025-5},
ISSN = {2190-6807},
year = {2016},
volume = {55},
editor = {Schoeberl, Martin},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.9},
URN = {urn:nbn:de:0030-drops-69028},
doi = {10.4230/OASIcs.WCET.2016.9},
annote = {Keywords: WCET, caches, AURIX, Automotive}
}
Document
Employing MPI Collectives for Timing Analysis on Embedded Multi-Cores
Abstract
Static WCET analysis of parallel programs running on shared-memory multicores suffers from high pessimism. Instead, distributed memory platforms which communicate via messages may be one solution for manycore systems. Message Passing Interface (MPI) is a standard for communication on these platforms. We show how its concept of collective operations can be employed for timing analysis. The idea is that the worst-case execution time (WCET) of a parallel program may be estimated by adding the WCET estimates of sequential program parts to the WCET estimates of communication parts. Therefore, we first analyse the two MPI operations MPI_Allreduce and MPI_Sendrecv. Employing these results, we make a timing analysis of the conjugate gradient (CG) benchmark from the NAS parallel benchmark suite.
Cite as
Martin Frieb, Alexander Stegmeier, Jörg Mische, and Theo Ungerer. Employing MPI Collectives for Timing Analysis on Embedded Multi-Cores. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016). Open Access Series in Informatics (OASIcs), Volume 55, pp. 10:1-10:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)
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@InProceedings{frieb_et_al:OASIcs.WCET.2016.10,
author = {Frieb, Martin and Stegmeier, Alexander and Mische, J\"{o}rg and Ungerer, Theo},
title = {{Employing MPI Collectives for Timing Analysis on Embedded Multi-Cores}},
booktitle = {16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
pages = {10:1--10:11},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-025-5},
ISSN = {2190-6807},
year = {2016},
volume = {55},
editor = {Schoeberl, Martin},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.10},
URN = {urn:nbn:de:0030-drops-69034},
doi = {10.4230/OASIcs.WCET.2016.10},
annote = {Keywords: Real Time, Network on Chip, WCET, Timing Analysis, MPI}
}
Document
Parallel Real-Time Tasks, as Viewed by WCET Analysis and Task Scheduling Approaches
Abstract
With the advent of multi-core platforms, research in the field of hard real-time has recently considered parallel software, from the perspective of both worst-case execution time (WCET) and task schedulability (or worst-case response time, WCRT) analyses. These two areas consider task models that are not completely identical and sometimes make different assumptions. This paper draws a brief overview of the state of the art in the timing analysis of parallel tasks and tries to identify points of convergence and divergence between the existing approaches.
Cite as
Christine Rochange. Parallel Real-Time Tasks, as Viewed by WCET Analysis and Task Scheduling Approaches. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016). Open Access Series in Informatics (OASIcs), Volume 55, pp. 11:1-11:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)
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@InProceedings{rochange:OASIcs.WCET.2016.11,
author = {Rochange, Christine},
title = {{Parallel Real-Time Tasks, as Viewed by WCET Analysis and Task Scheduling Approaches}},
booktitle = {16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
pages = {11:1--11:11},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-025-5},
ISSN = {2190-6807},
year = {2016},
volume = {55},
editor = {Schoeberl, Martin},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.11},
URN = {urn:nbn:de:0030-drops-69048},
doi = {10.4230/OASIcs.WCET.2016.11},
annote = {Keywords: multicore, parallel tasks, worst-case execution time analysis, schedulability, worst-case response time analysis}
}
Document
Understanding Shared Memory Bank Access Interference in Multi-Core Avionics
Abstract
Deployment of multi-core platforms in safety-critical applications requires reliable estimation of worst-case response time (WCRT) for critical processes. Determination of WCRT needs to accurately estimate and measure the interferences arising from multiple processes and multiple cores. Earlier works have proposed frameworks in which CPU, shared cache, and shared memory (DRAM) interferences can be estimated using some application and platform-dependent parameters. In this work we examine a recent work in which single core equivalent (SCE) worst case execution time is used as a basis for deriving WCRT. We describe the specific requirements in an avionics context including the sharing of memory banks by multiple processes on multiple cores, and adapt the SCE framework to account for them. We present the needed adaptations to a real-time operating system to enforce the requirements, and present a methodology for validating the theoretical WCRT through measurements on the resulting platform. The work reveals that the framework indeed creates a (pessimistic) bound on the WCRT. It also discloses that the maximum interference for memory accesses does not arise when all cores share the same memory bank.
Cite as
Andreas Löfwenmark and Simin Nadjm-Tehrani. Understanding Shared Memory Bank Access Interference in Multi-Core Avionics. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016). Open Access Series in Informatics (OASIcs), Volume 55, pp. 12:1-12:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)
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@InProceedings{lofwenmark_et_al:OASIcs.WCET.2016.12,
author = {L\"{o}fwenmark, Andreas and Nadjm-Tehrani, Simin},
title = {{Understanding Shared Memory Bank Access Interference in Multi-Core Avionics}},
booktitle = {16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
pages = {12:1--12:11},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-025-5},
ISSN = {2190-6807},
year = {2016},
volume = {55},
editor = {Schoeberl, Martin},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.12},
URN = {urn:nbn:de:0030-drops-69051},
doi = {10.4230/OASIcs.WCET.2016.12},
annote = {Keywords: multi-core, avionics, shared memory systems, WCET}
}