Reconfiguration Time Aware Processing on FPGAs

The possibility of partial reconfiguration of FPGAs during run-time can be used to implement systems that adapt their execution area over time. Two things are presented in this context: 1) For detailed investigations of partial reconfiguration, the two topics modeling and practical realization of reconfigurable systems must be rooted in the design process. We have developed a tool that meets this requirement. It eases the design of partial bitstreams for Xilinx FPGAs for research purpose. The tool wraps the obstacles of partial bitstream generation, motivating people new to this field. Moreover, the backend of the tool, a single UML class diagram that represents the whole characteristics of the reconfigurable system under development abstractly, allows to model reconfigurable systems in a comprehensive manner on a high level of abstraction. The UML diagram is filled during the design process until enough information for the generation of bitstreams is available. 2) In the single machine environment, several scheduling algorithms exist that allow to quantify schedules with respect to feasibility, optimality, etc. In contrast, reconfigurable devices execute tasks in parallel, which intentionally collides with the single machine principle and seems to require new methods and evaluation strategies for scheduling. However, the reconfiguration phases of adaptable architectures usually take place sequentially. Run-time adaptation is realized using an exclusive port, which is occupied for some reasonable time during reconfiguration. Thus, we can find an analogy to the single machine environment. We investigate the appliance of single processor scheduling algorithms to task reconfiguration on reconfigurable systems. We determine necessary adaptations and propose methods to evaluate the scheduling algorithms.