Volume

Dagstuhl Seminar Proceedings, Volume 6141

Publication Details

  • published at: 2006-10-09
  • Publisher: Schloss Dagstuhl – Leibniz-Zentrum für Informatik

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Document
DOI: 10.4230/DagSemProc.06141.1
06141 Abstracts Collection – Dynamically Reconfigurable Architectures

Authors: Jürgen Becker, Jürgen Teich, Gordon Brebner, and Peter M. Athanas

Abstract
From 02.04.06 to 07.04.06, the Dagstuhl Seminar 06141 ``Dynamically Reconfigurable Architectures'' was held in the International Conference and Research Center (IBFI), Schloss Dagstuhl. During the seminar, several participants presented their current research, and ongoing work and open problems were discussed. Abstracts of the presentations given during the seminar as well as abstracts of seminar results and ideas are put together in this paper. The first section describes the seminar topics and goals in general. Links to extended abstracts or full papers are provided, if available.
Cite as

Jürgen Becker, Jürgen Teich, Gordon Brebner, and Peter M. Athanas. 06141 Abstracts Collection – Dynamically Reconfigurable Architectures. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, pp. 1-26, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{becker_et_al:DagSemProc.06141.1,
  author =	{Becker, J\"{u}rgen and Teich, J\"{u}rgen and Brebner, Gordon and Athanas, Peter M.},
  title =	{{06141 Abstracts Collection – Dynamically Reconfigurable Architectures}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--26},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.1},
  URN =		{urn:nbn:de:0030-drops-8383},
  doi =		{10.4230/DagSemProc.06141.1},
  annote =	{Keywords: Dynamically run-time reconfigurable computing architectures, adaptive systems, computational models, circuit technologies, system architecture, CAD tool support}
}
Document
DOI: 10.4230/DagSemProc.06141.2
06141 Executive Summary – Dynamically Reconfigurable Architectures

Authors: Jürgen Becker, Jürgen Teich, Gordon Brebner, and Peter M. Athanas

Abstract
Dynamic and partial reconfiguration of hardware architectures such as FPGAs and XPPs brings an additional level of flexibility in the design of electronic systems by exploiting the possibility of configuring functions on-demand during run-time. This has led to many new ways of approaching existing research topics in the area of hardware design and optimization techniques. For example, the possibility of performing adaptation during run-time raises questions in the areas of dynamic control, real-time response, on-line power management and design complexity, since the reconfigurability increases the design space towards infinity. This Dagstuhl Seminar on Reconfigurable Architectures has aimed at raising a few of these topics e.g. on-line placement, pre-routing/on-line routing trade-off, power minimization etc., and also at presenting novel ideas on how to overcome the difficulties introduced in dynamic reconfigurable systems.
Cite as

Jürgen Becker, Jürgen Teich, Gordon Brebner, and Peter M. Athanas. 06141 Executive Summary – Dynamically Reconfigurable Architectures. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{becker_et_al:DagSemProc.06141.2,
  author =	{Becker, J\"{u}rgen and Teich, J\"{u}rgen and Brebner, Gordon and Athanas, Peter M.},
  title =	{{06141 Executive Summary – Dynamically Reconfigurable Architectures}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.2},
  URN =		{urn:nbn:de:0030-drops-8372},
  doi =		{10.4230/DagSemProc.06141.2},
  annote =	{Keywords: Reconfigurable Computing, Reconfigurable Supercomputing, Organic Computing, Dynamic Reconfiguration, Reconfigurable Hardware}
}
Document
DOI: 10.4230/DagSemProc.06141.3
A Reconfigurable Outer Modem Platform for Future Communications Systems

Authors: Norbert Wehn, Timo Vogt, and Christian Neeb

Abstract
Future mobile and wireless communications networks require flexible modem architectures with high performance. Efficient utilization of application specific flexibility is key to fulfill these requirements. For high throughput a single processor can not provide the necessary computational power. Hence multi-processor architectures become necessary. This paper presents a multi-processor platform based on a new dynamically reconfigurable application specific instruction set processor (dr-ASIP) for the application domain of channel decoding. Inherently parallel decoding tasks can be mapped onto individual processing nodes. The implied challenging inter-processor communication is efficiently handled by a Network-on-Chip (NoC) such that the throughput of each node is not degraded. The dr-ASIP features Viterbi and Log-MAP decoding for support of convolutional and turbo codes of more than 10 currently specified mobile and wireless standards. Furthermore, its flexibility allows for adaptation to future systems.
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Norbert Wehn, Timo Vogt, and Christian Neeb. A Reconfigurable Outer Modem Platform for Future Communications Systems. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, pp. 1-11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{wehn_et_al:DagSemProc.06141.3,
  author =	{Wehn, Norbert and Vogt, Timo and Neeb, Christian},
  title =	{{A Reconfigurable Outer Modem Platform for Future Communications Systems}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--11},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.3},
  URN =		{urn:nbn:de:0030-drops-7306},
  doi =		{10.4230/DagSemProc.06141.3},
  annote =	{Keywords: Domain-specific reconfigurable platform, channel coding, outer-modem}
}
Document
DOI: 10.4230/DagSemProc.06141.4
Analysis of Mojette Transform Implementation on Reconfigurable Hardware

Authors: József Vásárhelyi and Péter Serfözö

Abstract
Inscribing invisible marks (watermarking) into an image has different applications such as copyright, steganography or data integrity checking. Many different techniques have been employed for the last years in different spaces (Fourier, wavelet, Mojette domains, etc.). The presentation outline the development work related to create a functional block scheme of Mojette transform and Inverse Mojette transform using reconfigurable hardware.
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József Vásárhelyi and Péter Serfözö. Analysis of Mojette Transform Implementation on Reconfigurable Hardware. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, pp. 1-6, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{vasarhelyi_et_al:DagSemProc.06141.4,
  author =	{V\'{a}s\'{a}rhelyi, J\'{o}zsef and Serf\"{o}z\"{o}, P\'{e}ter},
  title =	{{Analysis of Mojette Transform Implementation on Reconfigurable Hardware}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--6},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.4},
  URN =		{urn:nbn:de:0030-drops-7465},
  doi =		{10.4230/DagSemProc.06141.4},
  annote =	{Keywords: Image processing, Mojette transformation}
}
Document
DOI: 10.4230/DagSemProc.06141.5
Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine

Authors: Diana Göhringer, Mateusz Majer, and Jürgen Teich

Abstract
We present an FPGA-based reconfigurable platform called Erlangen Slot Machine (ESM). The main advantages of this platform are: First, the possibility for each module to access peripherals independent from its location through a programmable crossbar, and local SRAM banks for individual modules. This physical design eases the implementation of run-time reconfigurable partial modules and enables an unrestricted relocation of modules on the device. We present our two-board ESM implementation and demonstrate a partially reconfigurable video filter application as well as a relocatable computer game including a dedicated inter-module communication scheme.
Cite as

Diana Göhringer, Mateusz Majer, and Jürgen Teich. Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, pp. 1-11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{gohringer_et_al:DagSemProc.06141.5,
  author =	{G\"{o}hringer, Diana and Majer, Mateusz and Teich, J\"{u}rgen},
  title =	{{Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--11},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.5},
  URN =		{urn:nbn:de:0030-drops-7369},
  doi =		{10.4230/DagSemProc.06141.5},
  annote =	{Keywords: FPGA-based reconfigurable platform, inter-module communication, crossbar, video filter demo}
}
Document
DOI: 10.4230/DagSemProc.06141.6
Dynamically Reconfigurable Systems-on-Chip

Authors: Walter Stechele

Abstract
The design space for dynamically reconfigurable SoCs can be seen in three dimensions: 1) the system architecture for computation and communication, ranging from dataflow-oriented dedicated logic blocks to instruction flow-oriented microprocessor cores, from dedicated point-to-point connections to Networks-on-Chip. 2) the granularity of reconfigurable elements, ranging from simple logic Look-Up-Tables to complex hardware accelerator engines and reconfigurable interconnect structures. 3) the configuration life cycle, ranging from application changes (in the order of seconds) to instruction-based reconfiguration (in the order of nanoseconds). We propose to use dynamically reconfigurable computing for video processing in driver assistance applications. In future automotive systems, video-based driver assistance will improve security. Video processing for driver assistance requires real time implementation of complex algorithms. A pure software implementation, based on low cost embedded CPUs in automotive environments, does not offer the required real time processing. Therefore hardware acceleration is necessary. Dedicated hardware circuits (ASICs) can offer the required real time processing, but they do not offer the necessary flexibility. Specific driving conditions, e.g. highway, country side, urban traffic, tunnel, require specific optimized algorithms. Reconfigurable hardware offers high potential for real time video processing and adaptability to various driving conditions. Our system architecture consists of embedded CPU cores for high-level application code, dedicated hardware accelerator engines for low level pixel processing, and an application-specific memory system. The hardware accelerators and the memory system are dynamically reconfigurable, i.e. hardware accelerator engines can be exchanged during runtime, controlled by the application code on the CPU. The life cycle of a configuration depends on the change of driving conditions. A requirement on the reconfiguration time is given by the frame rate of the video signal, e.g. 40 msec for the exchange and relocation of new engines.
Cite as

Walter Stechele. Dynamically Reconfigurable Systems-on-Chip. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, p. 1, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{stechele:DagSemProc.06141.6,
  author =	{Stechele, Walter},
  title =	{{Dynamically Reconfigurable Systems-on-Chip}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--1},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.6},
  URN =		{urn:nbn:de:0030-drops-7446},
  doi =		{10.4230/DagSemProc.06141.6},
  annote =	{Keywords: Dynamic reconfiguration, design space, video processing}
}
Document
DOI: 10.4230/DagSemProc.06141.7
Efficient architectures for streaming applications

Authors: Gerard J.M. Smit, Andre B. J. Kokkeler, Pascal T. Wolkotte, Marcel D. van de Burgwal, and Paul M. Heysters

Abstract
This presentation will focus on algorithms and reconfigurable tiled architectures for streaming DSP applications. The tile concept will not only be applied on chip level but also on board-level and system-level. The tile concept has a number of advantages: (1) depending on the requirements more or less tiles can be switched on/off, (2) the tile structure fits well to future IC process technologies, more tiles will be available in advanced process technologies, but the complexity per tile stays the same, (3) the tile concept is fault tolerant, faulty tiles can be discarded and (4) tiles can be configured in parallel. Because processing and memory is combined in the tiles, tasks can be executed efficiently on tiles (locality of reference). There are a number of application domains that can be considered as streaming DSP applications: for example wireless baseband processing (for HiperLAN/2, WiMax, DAB, DRM, DVB), multimedia processing (e.g. MPEG, MP3 coding/decoding), medical image processing, color image processing, sensor processing (e.g. remote surveillance cameras) and phased array radar systems. In this presentation the key characteristics of streaming DSP applications are highlighted, and the characteristics of the processing architectures to efficiently support these types of applications are addressed.
Cite as

Gerard J.M. Smit, Andre B. J. Kokkeler, Pascal T. Wolkotte, Marcel D. van de Burgwal, and Paul M. Heysters. Efficient architectures for streaming applications. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, pp. 1-7, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{smit_et_al:DagSemProc.06141.7,
  author =	{Smit, Gerard J.M. and Kokkeler, Andre B. J. and Wolkotte, Pascal T. and van de Burgwal, Marcel D. and Heysters, Paul M.},
  title =	{{Efficient architectures for streaming applications}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--7},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.7},
  URN =		{urn:nbn:de:0030-drops-7431},
  doi =		{10.4230/DagSemProc.06141.7},
  annote =	{Keywords: Reconfigurable streaming efficient}
}
Document
DOI: 10.4230/DagSemProc.06141.8
Enabling RTR for industry

Authors: Oliver Diessel and Shannon Koh

Abstract
This talk explores the promise of run tme reconfigurable (RTR) technology and makes an attempt to identify critical support elements that need to be put in place in order to overcome barriers to enhanced RTR uptake in industry. We outline a research project underway at the University of New South Wales to develop a positioning satellite receiver that exploits the diversity in satellite signals to mitigate the effects of interference. This project is examined as a case study to motivate the discovery of challenges an industrial organisation faces engineering a dynamically reconfigurable product. Our progress towards the development of a methodology for providing communications infrastructure for module-based applications illustrates one of the efforts necessary to develop useful synthesis tools for RTR applications development. We conclude with suggestions for how the academic community can better assist the commercial development of real applications.
Cite as

Oliver Diessel and Shannon Koh. Enabling RTR for industry. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, pp. 1-17, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{diessel_et_al:DagSemProc.06141.8,
  author =	{Diessel, Oliver and Koh, Shannon},
  title =	{{Enabling RTR for industry}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--17},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.8},
  URN =		{urn:nbn:de:0030-drops-7347},
  doi =		{10.4230/DagSemProc.06141.8},
  annote =	{Keywords: Run-time reconfiguration, industry support, design tools, module-based design, communications}
}
Document
DOI: 10.4230/DagSemProc.06141.9
FlexFilm - an Image Processor for Digital Film Processing

Authors: Sven Heithecker, Amilcar do Carmo Lucas, and Rolf Ernst

Abstract
Digital film processing is characterized by a resolution of at least 2K (2048x1536 pixels per frame at 30 bit/pixel and 24 pictures/s, data rate of 2.2 GBit/s); higher resolutions of 4K (8.8 GBit/s) and even 8K (35.2 GBit/s) are on their way. Real-time processing at this data rate is beyond the scope of today's standard and DSP processors, and ASICs are not economically viable due to the small market volume. Therefore, an FPGA-based approach was followed in the FlexFilm project. Different applications are supported on a single hardware platform by using different FPGA configurations. The multi-board, multi-FPGA hardware/software architecture is based on Xilinx Virtex-II Pro FPGAs which contain the reconfigurable image stream processing data path, large SDRAM memories for multiple frame storage and a PCI express communication backbone network. The FPGA-embedded CPU is used for control and less computation intensive tasks. This paper will focus on three key aspects: a) the used design methodology which combines macro component configuration and macro-level floorplanning with weak programmability using distributed microcoding, b) the global communication framework with communication scheduling and c) the configurable, multi-stream scheduling SDRAM controller with QoS support by access prioritization and traffic shaping. As an example, a complex noise reduction algorithm including a 2.5 dimensions DWT and a full 16x16 motion estimation at 24 fps requiring a total of 203 Gops/s net computing performance and a total of 28 Gbit/s DDR-SDRAM frame memory bandwidth will be shown.
Cite as

Sven Heithecker, Amilcar do Carmo Lucas, and Rolf Ernst. FlexFilm - an Image Processor for Digital Film Processing. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, pp. 1-11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{heithecker_et_al:DagSemProc.06141.9,
  author =	{Heithecker, Sven and do Carmo Lucas, Amilcar and Ernst, Rolf},
  title =	{{FlexFilm - an Image Processor for Digital Film Processing}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--11},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.9},
  URN =		{urn:nbn:de:0030-drops-7377},
  doi =		{10.4230/DagSemProc.06141.9},
  annote =	{Keywords: Digital film, FPGA, reconfigurable, stream-based architechture, weak programming, SDRAM-controller, QoS, communication centric, communication scheduli}
}
Document
DOI: 10.4230/DagSemProc.06141.10
Managing power amongst a group of networked embedded fpgas using dynamic reconfiguration and task migration

Authors: David Kearney and Mark Jasiunas

Abstract
Small unpiloted aircraft (UAVs) each have limited power budgets. If a group (swarm) of small UAVs is organized to perform a common task such as geo-location then it is possible to share the total power across the group by introducing task mobility inside the group supported by an ad hoc wireless network (where the communication encoding/decodeing is also done on fpgas). In this presentation I will describe research into the construction of a distributed operating system where partial dynamic reconfiguration and network mobility are combined so that fpga tasks can be moved to make the best use of the total power available in a swarm of UAVs.
Cite as

David Kearney and Mark Jasiunas. Managing power amongst a group of networked embedded fpgas using dynamic reconfiguration and task migration. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, pp. 1-9, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{kearney_et_al:DagSemProc.06141.10,
  author =	{Kearney, David and Jasiunas, Mark},
  title =	{{Managing power amongst a group of networked embedded fpgas using dynamic reconfiguration and task migration}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--9},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.10},
  URN =		{urn:nbn:de:0030-drops-7408},
  doi =		{10.4230/DagSemProc.06141.10},
  annote =	{Keywords: Dynamic reconfiguration unpiloted aircraft operating system}
}
Document
DOI: 10.4230/DagSemProc.06141.11
Physical 2D Morphware and Power Reduction Methods for Everyone

Authors: Jürgen Becker, Michael Hübner, and Katarina Paulsson

Abstract
Dynamic and partial reconfiguration discovers more and more the focus in academic and industrial research. Modern systems in e.g. avionic and automotive applications exploit the parallelism of hardware in order to reduce power consumption and to increase performance. State of the art reconfigurable FPGA devices allows reconfiguring parts of their architecture while the other configured architecture stays undisturbed in operation. This dynamic and partial reconfiguration allows therefore adapting the architecture to the requirements of the application while run-time. The difference to the traditional term of software and its related sequential architecture is the possibility to change the paradigm of brining the data to the respective processing elements. Dynamic and partial reconfiguration enables to bring the processing elements to the data and is therefore a new paradigm. The shift from the traditional microprocessor approaches with sequential processing of data to parallel processing reconfigurable architectures forces to introduce new paradigms with the focus on computing in time and space.
Cite as

Jürgen Becker, Michael Hübner, and Katarina Paulsson. Physical 2D Morphware and Power Reduction Methods for Everyone. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, pp. 1-5, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{becker_et_al:DagSemProc.06141.11,
  author =	{Becker, J\"{u}rgen and H\"{u}bner, Michael and Paulsson, Katarina},
  title =	{{Physical 2D Morphware and Power Reduction Methods for Everyone}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--5},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.11},
  URN =		{urn:nbn:de:0030-drops-7399},
  doi =		{10.4230/DagSemProc.06141.11},
  annote =	{Keywords: 2D online placement and routing, Reconfigurable Computing}
}
Document
DOI: 10.4230/DagSemProc.06141.12
Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System

Authors: Douglas Maskell and Timothy F. Oliver

Abstract
This paper presents a method of constructing pre-routed FPGA cores. This lays the foundations for a rapid system construction framework. There are two major challenges that need to be considered by this framework. The first is how to manage the wires crossing a core’s borders. The second is how to maintain an acceptable level of flexibility for system construction with only a minimum of overhead. Typical FPGA based systems are built up from cores developed by multiple third parties. Each compilation step that a developer performs before delivery adds value in terms of a cores performance, predictability and readiness for purpose. The perceived advantages of full independent core development are weighed against the loss in placement flexibility and elimination of the opportunities to optimise a system across cores. Few existing methodologies allow the independent compilation of FPGA cores through every step of the design flow. The wire detail of modern FPGA architectures is captured in a model that is used to analyse how the interconnect architecture effects the shape of pre-routed cores and the wire bandwidth available to interfaces. We have adapted academic placement and routing algorithms to our architectural model. The design flow has been modified to include a wire policy and interface constraints framework that tightly constrains the use of the wires that cross a core’s boundaries. Using this tool set we investigate the effect of pre-routing on overall system optimality. Compiling a set of example systems using the pre-routed approach shows only a 2% increase in total wire use over the pre-placed approach. Place and route times are vastly reduced for systems composed of regular modules. Being able to break a system into independent cores reduces the placement and routing time even for non-regular systems, and will open opportunities for its possible use in resource constrained embedded systems.
Cite as

Douglas Maskell and Timothy F. Oliver. Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, pp. 1-10, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{maskell_et_al:DagSemProc.06141.12,
  author =	{Maskell, Douglas and Oliver, Timothy F.},
  title =	{{Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--10},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.12},
  URN =		{urn:nbn:de:0030-drops-7410},
  doi =		{10.4230/DagSemProc.06141.12},
  annote =	{Keywords: Dynamic Reconfiguration, Rapid Construction, FPGA Routing matrix}
}
Document
DOI: 10.4230/DagSemProc.06141.13
QUKU: A Coarse Grained Paradigm for FPGAs

Authors: Sunil Shukla, Neil W. Bergmann, and Jürgen Becker

Abstract
To fill the gap between increasing demand for reconfigurability and performance efficiency, CGRAs are seen to be an emerging platform. The advantage lies in quick dynamic reconfiguration and power efficiency. Despite having these advantages they have failed to show their mark. This paper describes the QUKU architecture, which uses a coarse-grained dynamically reconfigurable PE array (CGRA) overlaid on an FPGA. The low-speed reconfigurability of the FPGA is used to optimize the CGRA for different applications, whilst the high-speed CGRA reconfiguration is used within an application for operator re-use.
Cite as

Sunil Shukla, Neil W. Bergmann, and Jürgen Becker. QUKU: A Coarse Grained Paradigm for FPGAs. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, pp. 1-8, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{shukla_et_al:DagSemProc.06141.13,
  author =	{Shukla, Sunil and Bergmann, Neil W. and Becker, J\"{u}rgen},
  title =	{{QUKU: A Coarse Grained Paradigm for FPGAs}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--8},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.13},
  URN =		{urn:nbn:de:0030-drops-7424},
  doi =		{10.4230/DagSemProc.06141.13},
  annote =	{Keywords: FPGA, CGRA, Reconfiguration}
}
Document
DOI: 10.4230/DagSemProc.06141.14
Reconfigurable Architectures and Instruction Sets: Programmability, Code Generation, and Program Execution

Authors: Rainer Buchty

Abstract
Within Self-reconfiguring systems two basic problems arise: firstly, on instruction level reconfigurable instruction sets make program generation and execution inherently difficult. Secondly, reconfiguration must not violate certain restrictions vital for the running application. We describe a combined low-overhead approach which targets both problems by instrumenting an attributed low-overhead run-time environment which is able to dynamically map application-specific instructions to a variety of implementation alternatives while strictly adhering to given application demands. Our approach can be used application-independent and is suitable for use within the adaptive planning stage of a Self-X system as demonstrated by a reference implementation.
Cite as

Rainer Buchty. Reconfigurable Architectures and Instruction Sets: Programmability, Code Generation, and Program Execution. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, pp. 1-4, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{buchty:DagSemProc.06141.14,
  author =	{Buchty, Rainer},
  title =	{{Reconfigurable Architectures and Instruction Sets: Programmability, Code Generation, and Program Execution}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--4},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.14},
  URN =		{urn:nbn:de:0030-drops-7331},
  doi =		{10.4230/DagSemProc.06141.14},
  annote =	{Keywords: Self-X, Instruction Set Reconfiguration, Run-time Environment, Code Generation, Programming}
}
Document
DOI: 10.4230/DagSemProc.06141.15
Reconfigurable Processing Units vs. Reconfigurable Interconnects

Authors: Andreas Herkersdorf, Christopher Claus, Michael Meitinger, Rainer Ohlendorf, and Thomas Wild

Abstract
The question we proposed to explore with the seminar participants is whether the dynamic reconfigurable computing community is paying sufficient attention to the subject of dynamic reconfigurable SoC interconnects. By SoC interconnect, we refer to architecture- or system-level building blocks such as on-chip buses, crossbars, add-drop rings or meshed NoCs. P Our motivation to systematically investigate this question originates from conceptual and architectural challenges in the FlexPath project. FlexPath is a new Network Processor architecture that flexibly maps networking functions onto both SW programmable CPU resources and (re-)configurable HW building blocks in a way that different packet flows are forwarded via different, optimized processing paths. Packets with well defined processing requirements may even bypass the central CPU complex (AutoRoute). In consequence, CPU processing resources are more effectively used and the overall NP throughput is improved compared to conventional NPU architectures. P The following requirements apply with respect to the dynamic adaptation of the processing paths: The rule basis for NPU-internal processing path lookup is updated in the order of 100us, packet inter-arrival time is in the order of 100ns. Partial reconfiguration of the rule basis (and/or interconnect structure) with state of the art techniques would take several ms resulting in a continuously blocked system. However, performing path selection with conventional lookup table search and updates (and a statically configured on-chip bus) takes considerably less than 100ns. Hence, is there a need for new conceptual approaches with respect to dynamic SoC interconnect reconfiguration, or is this a ''no issue'' as conventional techniques are sufficient?
Cite as

Andreas Herkersdorf, Christopher Claus, Michael Meitinger, Rainer Ohlendorf, and Thomas Wild. Reconfigurable Processing Units vs. Reconfigurable Interconnects. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, pp. 1-3, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{herkersdorf_et_al:DagSemProc.06141.15,
  author =	{Herkersdorf, Andreas and Claus, Christopher and Meitinger, Michael and Ohlendorf, Rainer and Wild, Thomas},
  title =	{{Reconfigurable Processing Units vs. Reconfigurable Interconnects}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--3},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.15},
  URN =		{urn:nbn:de:0030-drops-7797},
  doi =		{10.4230/DagSemProc.06141.15},
  annote =	{Keywords: Reconfigurable SoC interconnect}
}
Document
DOI: 10.4230/DagSemProc.06141.16
Reconfiguration Time Aware Processing on FPGAs

Authors: Florian Dittmann

Abstract
The possibility of partial reconfiguration of FPGAs during run-time can be used to implement systems that adapt their execution area over time. Two things are presented in this context: 1) For detailed investigations of partial reconfiguration, the two topics modeling and practical realization of reconfigurable systems must be rooted in the design process. We have developed a tool that meets this requirement. It eases the design of partial bitstreams for Xilinx FPGAs for research purpose. The tool wraps the obstacles of partial bitstream generation, motivating people new to this field. Moreover, the backend of the tool, a single UML class diagram that represents the whole characteristics of the reconfigurable system under development abstractly, allows to model reconfigurable systems in a comprehensive manner on a high level of abstraction. The UML diagram is filled during the design process until enough information for the generation of bitstreams is available. 2) In the single machine environment, several scheduling algorithms exist that allow to quantify schedules with respect to feasibility, optimality, etc. In contrast, reconfigurable devices execute tasks in parallel, which intentionally collides with the single machine principle and seems to require new methods and evaluation strategies for scheduling. However, the reconfiguration phases of adaptable architectures usually take place sequentially. Run-time adaptation is realized using an exclusive port, which is occupied for some reasonable time during reconfiguration. Thus, we can find an analogy to the single machine environment. We investigate the appliance of single processor scheduling algorithms to task reconfiguration on reconfigurable systems. We determine necessary adaptations and propose methods to evaluate the scheduling algorithms.
Cite as

Florian Dittmann. Reconfiguration Time Aware Processing on FPGAs. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, pp. 1-12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{dittmann:DagSemProc.06141.16,
  author =	{Dittmann, Florian},
  title =	{{Reconfiguration Time Aware Processing on FPGAs}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--12},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.16},
  URN =		{urn:nbn:de:0030-drops-7351},
  doi =		{10.4230/DagSemProc.06141.16},
  annote =	{Keywords: Real-Time, Partial Reconfiguration, Reconfiguration Time Scheduling}
}
Document
DOI: 10.4230/DagSemProc.06141.17
Reliability-Aware Power Management Of Multi-Core Systems (MPSoCs)

Authors: Klaus Waldschmidt, Jan Haase, Andreas Hofmann, Markus Damm, and Dennis Hauser

Abstract
Long-term reliability of processors in embedded systems is experiencing growing attention since decreasing feature sizes and increasing power consumption have a negative influence on the lifespan. Among other measures, the reliability can be influenced significantly by Dynamic Power Management (DPM), since it affects the processor's temperature. Compared to single-core systems reconfigurable multi-core SoCs offer much more possibilities to optimize power and reliability. The impact of different DPM-strategies on the lifespan of multi-core processors is the focus of this presentation. It is shown that the long-term reliability of a multi-core system can be influenced deliberately with different DPM strategies and that temperature cycling greatly influences the estimated lifespan. In this presentation, a new reliability-aware dynamic power management (RADPM) policy is explained.
Cite as

Klaus Waldschmidt, Jan Haase, Andreas Hofmann, Markus Damm, and Dennis Hauser. Reliability-Aware Power Management Of Multi-Core Systems (MPSoCs). In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, pp. 1-7, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{waldschmidt_et_al:DagSemProc.06141.17,
  author =	{Waldschmidt, Klaus and Haase, Jan and Hofmann, Andreas and Damm, Markus and Hauser, Dennis},
  title =	{{Reliability-Aware Power Management Of Multi-Core Systems (MPSoCs)}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--7},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.17},
  URN =		{urn:nbn:de:0030-drops-7458},
  doi =		{10.4230/DagSemProc.06141.17},
  annote =	{Keywords: Organic computing, Adaptivity, Power Management, Power Consumption, Reliability, SDVM}
}
Document
DOI: 10.4230/DagSemProc.06141.18
The (empty?) Promise of FPGA Supercomputing

Authors: Peter M. Athanas

Abstract
There have been some notable success stories in the past that give merit to the viability of the creation of an FPGA-based supercomputer. When examining the computing potential of these devices, they appear to offer competitive computational characteristics that are highly competitive to contemporary high-performance processors. Recently, there have been supercomputer-class processing blades offered by the leading high-performance computing specialist, yet the sales of these nodes have been less than spectacular. This talk examines why this may be the case, and explores the viability and cost-performance of FPGA-based supercomputers.
Cite as

Peter M. Athanas. The (empty?) Promise of FPGA Supercomputing. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, pp. 1-13, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{athanas:DagSemProc.06141.18,
  author =	{Athanas, Peter M.},
  title =	{{The (empty?) Promise of FPGA Supercomputing}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--13},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.18},
  URN =		{urn:nbn:de:0030-drops-7320},
  doi =		{10.4230/DagSemProc.06141.18},
  annote =	{Keywords: FPGA supercomputing}
}
Document
DOI: 10.4230/DagSemProc.06141.19
Towards an Automated Design of Application-specific Reconfigurable Logic

Authors: Peter Zipf and Manfred Glesner

Abstract
Reconfigurable logic is known to have the potential to provide better solutions than direct ASIC implementations or processors in some situations. A necessary prerequisite for area advantages compared to ASICs or a better energy efficiency than processors is an application specific design of the reconfigurable unit. Adapting it to the specific requirements of an application helps to compensate for the area and speed penalty introduced by reconfigurability. The data paths of reconfigurable units are best suited for data flow oriented tasks, but for many applications, both control flow and data flow must be handled, so a integration of the reconfigurable unit into a processor environment is an appropriate choice. By analysing the existing design flow and integration possibilities for reconfigurable units, a basis for discussing possible automation schemes and a standardised interface is defined. Possible future research could investigate an automated design support for the building blocks of reconfigurable units and the definition of a standard processor interface for some classes of reconfigurable units.
Cite as

Peter Zipf and Manfred Glesner. Towards an Automated Design of Application-specific Reconfigurable Logic. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, pp. 1-2, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{zipf_et_al:DagSemProc.06141.19,
  author =	{Zipf, Peter and Glesner, Manfred},
  title =	{{Towards an Automated Design of Application-specific Reconfigurable Logic}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--2},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.19},
  URN =		{urn:nbn:de:0030-drops-7319},
  doi =		{10.4230/DagSemProc.06141.19},
  annote =	{Keywords: Application-specific reconfigurable units, processor integration, design automation}
}

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  • Athanas, Peter M.
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  • Buchty, Rainer
  • C
  • Claus, Christopher
  • D
  • Damm, Markus
  • Diessel, Oliver
  • Dittmann, Florian
  • do Carmo Lucas, Amilcar
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  • Ernst, Rolf
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  • Glesner, Manfred
  • Göhringer, Diana
  • H
  • Haase, Jan
  • Hauser, Dennis
  • Heithecker, Sven
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  • Heysters, Paul M.
  • Hofmann, Andreas
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