<h2>Dagstuhl Seminar Proceedings, Volume 6141, </h2>
<ul>
<li>
<span class="authors">Jürgen Becker, Jürgen Teich, Gordon Brebner, and Peter M. Athanas</span>
<span class="title">06141 Abstracts Collection – Dynamically Reconfigurable Architectures</span>
<a class="doi" href="https://doi.org/10.4230/DagSemProc.06141.1">10.4230/DagSemProc.06141.1</a>
</li>
<li>
<span class="authors">Jürgen Becker, Jürgen Teich, Gordon Brebner, and Peter M. Athanas</span>
<span class="title">06141 Executive Summary – Dynamically Reconfigurable Architectures</span>
<a class="doi" href="https://doi.org/10.4230/DagSemProc.06141.2">10.4230/DagSemProc.06141.2</a>
</li>
<li>
<span class="authors">Norbert Wehn, Timo Vogt, and Christian Neeb</span>
<span class="title">A Reconfigurable Outer Modem Platform for Future Communications Systems</span>
<a class="doi" href="https://doi.org/10.4230/DagSemProc.06141.3">10.4230/DagSemProc.06141.3</a>
</li>
<li>
<span class="authors">József Vásárhelyi and Péter Serfözö</span>
<span class="title">Analysis of Mojette Transform Implementation on Reconfigurable Hardware</span>
<a class="doi" href="https://doi.org/10.4230/DagSemProc.06141.4">10.4230/DagSemProc.06141.4</a>
</li>
<li>
<span class="authors">Diana Göhringer, Mateusz Majer, and Jürgen Teich</span>
<span class="title">Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine</span>
<a class="doi" href="https://doi.org/10.4230/DagSemProc.06141.5">10.4230/DagSemProc.06141.5</a>
</li>
<li>
<span class="authors">Walter Stechele</span>
<span class="title">Dynamically Reconfigurable Systems-on-Chip</span>
<a class="doi" href="https://doi.org/10.4230/DagSemProc.06141.6">10.4230/DagSemProc.06141.6</a>
</li>
<li>
<span class="authors">Gerard J.M. Smit, Andre B. J. Kokkeler, Pascal T. Wolkotte, Marcel D. van de Burgwal, and Paul M. Heysters</span>
<span class="title">Efficient architectures for streaming applications</span>
<a class="doi" href="https://doi.org/10.4230/DagSemProc.06141.7">10.4230/DagSemProc.06141.7</a>
</li>
<li>
<span class="authors">Oliver Diessel and Shannon Koh</span>
<span class="title">Enabling RTR for industry</span>
<a class="doi" href="https://doi.org/10.4230/DagSemProc.06141.8">10.4230/DagSemProc.06141.8</a>
</li>
<li>
<span class="authors">Sven Heithecker, Amilcar do Carmo Lucas, and Rolf Ernst</span>
<span class="title">FlexFilm - an Image Processor for Digital Film Processing</span>
<a class="doi" href="https://doi.org/10.4230/DagSemProc.06141.9">10.4230/DagSemProc.06141.9</a>
</li>
<li>
<span class="authors">David Kearney and Mark Jasiunas</span>
<span class="title">Managing power amongst a group of networked embedded fpgas using dynamic reconfiguration and task migration</span>
<a class="doi" href="https://doi.org/10.4230/DagSemProc.06141.10">10.4230/DagSemProc.06141.10</a>
</li>
<li>
<span class="authors">Jürgen Becker, Michael Hübner, and Katarina Paulsson</span>
<span class="title">Physical 2D Morphware and Power Reduction Methods for Everyone</span>
<a class="doi" href="https://doi.org/10.4230/DagSemProc.06141.11">10.4230/DagSemProc.06141.11</a>
</li>
<li>
<span class="authors">Douglas Maskell and Timothy F. Oliver</span>
<span class="title">Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System</span>
<a class="doi" href="https://doi.org/10.4230/DagSemProc.06141.12">10.4230/DagSemProc.06141.12</a>
</li>
<li>
<span class="authors">Sunil Shukla, Neil W. Bergmann, and Jürgen Becker</span>
<span class="title">QUKU: A Coarse Grained Paradigm for FPGAs</span>
<a class="doi" href="https://doi.org/10.4230/DagSemProc.06141.13">10.4230/DagSemProc.06141.13</a>
</li>
<li>
<span class="authors">Rainer Buchty</span>
<span class="title">Reconfigurable Architectures and Instruction Sets: Programmability, Code Generation, and Program Execution</span>
<a class="doi" href="https://doi.org/10.4230/DagSemProc.06141.14">10.4230/DagSemProc.06141.14</a>
</li>
<li>
<span class="authors">Andreas Herkersdorf, Christopher Claus, Michael Meitinger, Rainer Ohlendorf, and Thomas Wild</span>
<span class="title">Reconfigurable Processing Units vs. Reconfigurable Interconnects</span>
<a class="doi" href="https://doi.org/10.4230/DagSemProc.06141.15">10.4230/DagSemProc.06141.15</a>
</li>
<li>
<span class="authors">Florian Dittmann</span>
<span class="title">Reconfiguration Time Aware Processing on FPGAs</span>
<a class="doi" href="https://doi.org/10.4230/DagSemProc.06141.16">10.4230/DagSemProc.06141.16</a>
</li>
<li>
<span class="authors">Klaus Waldschmidt, Jan Haase, Andreas Hofmann, Markus Damm, and Dennis Hauser</span>
<span class="title">Reliability-Aware Power Management Of Multi-Core Systems (MPSoCs)</span>
<a class="doi" href="https://doi.org/10.4230/DagSemProc.06141.17">10.4230/DagSemProc.06141.17</a>
</li>
<li>
<span class="authors">Peter M. Athanas</span>
<span class="title">The (empty?) Promise of FPGA Supercomputing</span>
<a class="doi" href="https://doi.org/10.4230/DagSemProc.06141.18">10.4230/DagSemProc.06141.18</a>
</li>
<li>
<span class="authors">Peter Zipf and Manfred Glesner</span>
<span class="title">Towards an Automated Design of Application-specific Reconfigurable Logic</span>
<a class="doi" href="https://doi.org/10.4230/DagSemProc.06141.19">10.4230/DagSemProc.06141.19</a>
</li>
</ul>
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