Compiler-Driven Power Optimizations in the Register File of Processor-Based Systems

Authors José Luis Ayala, Marisa Lópes-Vallejo

Thumbnail PDF


  • Filesize: 336 kB
  • 17 pages

Document Identifiers

Author Details

José Luis Ayala
Marisa Lópes-Vallejo

Cite AsGet BibTex

José Luis Ayala and Marisa Lópes-Vallejo. Compiler-Driven Power Optimizations in the Register File of Processor-Based Systems. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 5141, pp. 1-17, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2005)


The complexity of the register file is currently one of the main factors on determining the cycle time of high performance wide-issue microprocessors due to its access time and size. Both parameters are directly related to the number of read and write ports of the register file and can be managed from a code compilation-level. Therefore, it is a priority goal to reduce this complexity in order to allow the efficient implementation of complex superscalar machines. This work presents a modified register assignment and a banked architecture which efficiently reduce the number of required ports. Also, the effect of the loop unrollling optimization performed by the compiler is analyzed and several power-efficient modifications to this mechanism are proposed. Both register assignment and loop unrolling mechanisms are modified to improve the energy savings while avoiding a hard performance impact.
  • Register file
  • power reduction
  • compiler optimization
  • loop unrolling
  • banked architecture


  • Access Statistics
  • Total Accesses (updated on a weekly basis)
    PDF Downloads
Questions / Remarks / Feedback

Feedback for Dagstuhl Publishing

Thanks for your feedback!

Feedback submitted

Could not send message

Please try again later or send an E-mail