Volume

Dagstuhl Seminar Proceedings, Volume 5141

Publication Details

  • published at: 2005-11-02
  • Publisher: Schloss Dagstuhl – Leibniz-Zentrum für Informatik

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Document
DOI: 10.4230/DagSemProc.05141.1
05141 Abstracts Collection – Power-aware Computing Systems

Authors: Luca Benini, Ulrich Kremer, Christian W. Probst, and Peter Schelkens

Abstract
From 03.04.05 to 08.04.05, the Dagstuhl Seminar 05141 ``Power-aware Computing Systems'' was held in the International Conference and Research Center (IBFI), Schloss Dagstuhl. During the seminar, several participants presented their current research, and ongoing work and discussed open problems. Abstracts of the presentations given during the seminar as well as abstracts of seminar results and ideas are collected in this paper. The first section describes the seminar topics and goals. Links to extended abstracts or full papers are provided, if available.
Cite as

Luca Benini, Ulrich Kremer, Christian W. Probst, and Peter Schelkens. 05141 Abstracts Collection – Power-aware Computing Systems. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 5141, pp. 1-14, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2005)

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@InProceedings{benini_et_al:DagSemProc.05141.1,
  author =	{Benini, Luca and Kremer, Ulrich and Probst, Christian W. and Schelkens, Peter},
  title =	{{05141 Abstracts Collection – Power-aware Computing Systems}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--14},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2005},
  volume =	{5141},
  editor =	{Luca Benini and Ulrich Kremer and Christian W. Probst and Peter Schelkens},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.05141.1},
  URN =		{urn:nbn:de:0030-drops-3108},
  doi =		{10.4230/DagSemProc.05141.1},
  annote =	{Keywords: Energy dissipation, power reduction, measurement, management, performance}
}
Document
DOI: 10.4230/DagSemProc.05141.2
05141 Summary – Power-aware Computing Systems

Authors: Luca Benini, Ulrich Kremer, Christian W. Probst, and Peter Schelkens

Abstract
This paper summarizes the objectives and structure of a seminar with the same title, held from April 3rd to April 8th 2005 at Schloss Dagstuhl, Germany.
Cite as

Luca Benini, Ulrich Kremer, Christian W. Probst, and Peter Schelkens. 05141 Summary – Power-aware Computing Systems. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 5141, pp. 1-7, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2005)

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@InProceedings{benini_et_al:DagSemProc.05141.2,
  author =	{Benini, Luca and Kremer, Ulrich and Probst, Christian W. and Schelkens, Peter},
  title =	{{05141 Summary – Power-aware Computing Systems}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--7},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2005},
  volume =	{5141},
  editor =	{Luca Benini and Ulrich Kremer and Christian W. Probst and Peter Schelkens},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.05141.2},
  URN =		{urn:nbn:de:0030-drops-3216},
  doi =		{10.4230/DagSemProc.05141.2},
  annote =	{Keywords: Power-aware architectures}
}
Document
DOI: 10.4230/DagSemProc.05141.3
A Multilevel Introspective Dynamic Optimization System For Holistic Power-Aware Computing

Authors: Vasanth Venkatachalam, Christian W. Probst, and Michael Franz

Abstract
Power consumption is rapidly becoming the dominant limiting factor for further improvements in computer design. Curiously, this applies both at the "high end" of workstations and servers and the "low end" of handheld devices and embedded computers. At the high-end, the challenge lies in dealing with exponentially growing power densities. At the low-end, there is a demand to make mobile devices more powerful and longer lasting, but battery technology is not improving at the same rate that power consumption is rising. Traditional power-management research is fragmented; techniques are being developed at specific levels, without fully exploring their synergy with other levels. Most software techniques target either operating systems or compilers but do not explore the interaction between the two layers. These techniques also have not fully explored the potential of virtual machines for power management. In contrast, we are developing a system that integrates information from multiple levels of software and hardware, connecting these levels through a communication channel. At the heart of this system are a virtual machine that compiles and dynamically profiles code, and an optimizer that reoptimizes all code, including that of applications and the virtual machine itself. We believe this introspective, holistic approach enables more informed power-management decisions.
Cite as

Vasanth Venkatachalam, Christian W. Probst, and Michael Franz. A Multilevel Introspective Dynamic Optimization System For Holistic Power-Aware Computing. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 5141, pp. 1-14, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2005)

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@InProceedings{venkatachalam_et_al:DagSemProc.05141.3,
  author =	{Venkatachalam, Vasanth and Probst, Christian W. and Franz, Michael},
  title =	{{A Multilevel Introspective Dynamic Optimization System For Holistic Power-Aware Computing}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--14},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2005},
  volume =	{5141},
  editor =	{Luca Benini and Ulrich Kremer and Christian W. Probst and Peter Schelkens},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.05141.3},
  URN =		{urn:nbn:de:0030-drops-3099},
  doi =		{10.4230/DagSemProc.05141.3},
  annote =	{Keywords: Power-aware Computing, Virtual Machines, Dynamic Optimization}
}
Document
DOI: 10.4230/DagSemProc.05141.4
Compiler-Driven Power Optimizations in the Register File of Processor-Based Systems

Authors: José Luis Ayala and Marisa Lópes-Vallejo

Abstract
The complexity of the register file is currently one of the main factors on determining the cycle time of high performance wide-issue microprocessors due to its access time and size. Both parameters are directly related to the number of read and write ports of the register file and can be managed from a code compilation-level. Therefore, it is a priority goal to reduce this complexity in order to allow the efficient implementation of complex superscalar machines. This work presents a modified register assignment and a banked architecture which efficiently reduce the number of required ports. Also, the effect of the loop unrollling optimization performed by the compiler is analyzed and several power-efficient modifications to this mechanism are proposed. Both register assignment and loop unrolling mechanisms are modified to improve the energy savings while avoiding a hard performance impact.
Cite as

José Luis Ayala and Marisa Lópes-Vallejo. Compiler-Driven Power Optimizations in the Register File of Processor-Based Systems. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 5141, pp. 1-17, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2005)

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@InProceedings{ayala_et_al:DagSemProc.05141.4,
  author =	{Ayala, Jos\'{e} Luis and L\'{o}pes-Vallejo, Marisa},
  title =	{{Compiler-Driven Power Optimizations in the Register File of Processor-Based Systems}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--17},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2005},
  volume =	{5141},
  editor =	{Luca Benini and Ulrich Kremer and Christian W. Probst and Peter Schelkens},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.05141.4},
  URN =		{urn:nbn:de:0030-drops-3053},
  doi =		{10.4230/DagSemProc.05141.4},
  annote =	{Keywords: Register file, power reduction, compiler optimization, loop unrolling, banked architecture}
}
Document
DOI: 10.4230/DagSemProc.05141.5
Energy Conservation in Memory Hierarchies using Power-Aware Cached-DRAM

Authors: Daniel Mossé, Nevine AbouGhazaleh, Bruce Childers, and Rami Melhem

Abstract
Main memory has become one of the largest contributors to overall energy consumption and offers many opportunities for power/energy reduction. In this paper, we propose a new memory organization, called {em Power-Aware Cached-DRAM} (PA-CDRAM), that integrates a moderately sized cache directly into a memory device. We use this cache to turn a memory bank off immediately after a memory access to reduce energy consumption. While other work has used CDRAM to improve memory performance, we modify CDRAM to reduce energy consumption. In this paper, we describe our memory organization and describe the challenges for achieving low energy consumption and how to address them. We evaluate the approach using a cycle accurate processor and memory simulator. Our results show that PA-CDRAM achieves an average 28% improvement in the energy-delay product when compared to a time-out power management technique.
Cite as

Daniel Mossé, Nevine AbouGhazaleh, Bruce Childers, and Rami Melhem. Energy Conservation in Memory Hierarchies using Power-Aware Cached-DRAM. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 5141, pp. 1-10, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2005)

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@InProceedings{mosse_et_al:DagSemProc.05141.5,
  author =	{Moss\'{e}, Daniel and AbouGhazaleh, Nevine and Childers, Bruce and Melhem, Rami},
  title =	{{Energy Conservation in Memory Hierarchies using Power-Aware Cached-DRAM}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--10},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2005},
  volume =	{5141},
  editor =	{Luca Benini and Ulrich Kremer and Christian W. Probst and Peter Schelkens},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.05141.5},
  URN =		{urn:nbn:de:0030-drops-3049},
  doi =		{10.4230/DagSemProc.05141.5},
  annote =	{Keywords: Memory power management, cached DRAM}
}
Document
DOI: 10.4230/DagSemProc.05141.6
Inter-program Optimizations for Disk Energy Reduction

Authors: Jerry Hom and Ulrich Kremer

Abstract
Compiler support for power and energy management has been shown to be effective in reducing overall power dissipation and energy consumption of programs, for instance through compiler-directed resource hibernation and dynamic frequency and voltage scaling. The multi-programming model with virtual memory presents a virtualized view of the machine such that compilers typically take single programs as input, without the knowledge of other programs that may run at the same time on the target machine. This work investigates the benefits of optimizing sets of programs with the goal of reducing overall disk energy. The two key ideas are to synchronize the disk accesses across a group of programs thereby allowing longer disk idle periods, and to utilize execution context knowledge to allocate maximal buffer sizes. The compiler inserts runtime system calls for profiling the application and disk, uses execution context in allocating buffers, and synchronizes disk accesses with an inverse barrier policy. Data prefetching has been added to mitigate the overhead of synchronization. Experimental results are based on three streaming applications and their subsets. The experiments show that inter-program optimizations can have significant disk energy savings over individually optimized programs. Applying the most aggressive inter-program optimizations result in energy savings of up to 49%, and saving 34% on average.
Cite as

Jerry Hom and Ulrich Kremer. Inter-program Optimizations for Disk Energy Reduction. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 5141, pp. 1-15, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2005)

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@InProceedings{hom_et_al:DagSemProc.05141.6,
  author =	{Hom, Jerry and Kremer, Ulrich},
  title =	{{Inter-program Optimizations for Disk Energy Reduction}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--15},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2005},
  volume =	{5141},
  editor =	{Luca Benini and Ulrich Kremer and Christian W. Probst and Peter Schelkens},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.05141.6},
  URN =		{urn:nbn:de:0030-drops-3086},
  doi =		{10.4230/DagSemProc.05141.6},
  annote =	{Keywords: Compiler, inter-program, optimization, execution context, synchronization, inverse barrier}
}
Document
DOI: 10.4230/DagSemProc.05141.7
Methodologies for Designing Power-Aware Smart Card Systems

Authors: Christian Steger, Ulrich Neffe, Klaus Rothbart, Andreas Mühlberger, Edgar Rieger, and Reinhold Weiss

Abstract
Smart cards are some of the smallest computing platforms in use today. They have limited resources, but a huge number of functional requirements. The requirement for multi-application cards increases the demand for high performance and security even more, whereas the limits given by size and energy consumption remain constant. We describe new methodologies for designing and implementing entire systems with regard to power awareness and required performance. To make use of this power-saving potential, also the higher layers of the system - the operating system layer and the application domain layer - are required to be designed together with the rest of the system. HW/SW co-design methodologies enable the gain of system-level optimization. The first part presents the abstraction of smart cards to optimize system architecture and memory system. Both functional and transactional-level models are presented and discussed. The proposed design flow and preliminary results of the evaluation are depicted. Another central part of this methodology is a cycle-accurate instruction-set simulator for secure software development. The underlaying energy model is designed to decouple instruction and data dependent energy dissipation, which leads to an independent characterization process and allows stepwise model refinement to increase estimation accuracy. The model has been evaluated for a high-performance smart card CPU and an use-case for secure software is given.
Cite as

Christian Steger, Ulrich Neffe, Klaus Rothbart, Andreas Mühlberger, Edgar Rieger, and Reinhold Weiss. Methodologies for Designing Power-Aware Smart Card Systems. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 5141, pp. 1-12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2005)

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@InProceedings{steger_et_al:DagSemProc.05141.7,
  author =	{Steger, Christian and Neffe, Ulrich and Rothbart, Klaus and M\"{u}hlberger, Andreas and Rieger, Edgar and Weiss, Reinhold},
  title =	{{Methodologies for Designing Power-Aware Smart Card Systems}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--12},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2005},
  volume =	{5141},
  editor =	{Luca Benini and Ulrich Kremer and Christian W. Probst and Peter Schelkens},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.05141.7},
  URN =		{urn:nbn:de:0030-drops-3067},
  doi =		{10.4230/DagSemProc.05141.7},
  annote =	{Keywords: Smart cards, power awareness, HW/SW codesign, cycle-accurate instruction-set simulator}
}
Document
DOI: 10.4230/DagSemProc.05141.8
Power Optimization in advanced Channel Coding

Authors: Norbert Wehn

Abstract
Channel Coding is an important building block in the outer modem of baseband processing of wireless communication systems. Turbo-Codes and LDPC codes are the most efficient coding techniques known today. They are already in use of many standards e.g. UMTS, DVB and in discussion for emerging standards e.g. WLAN. The implementation of these coding techniques implies many challenges. In this talk we will discuss some of these challenges and will put special emphasis on low power implementations.
Cite as

Norbert Wehn. Power Optimization in advanced Channel Coding. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 5141, pp. 1-4, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2005)

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@InProceedings{wehn:DagSemProc.05141.8,
  author =	{Wehn, Norbert},
  title =	{{Power Optimization in advanced Channel Coding}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--4},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2005},
  volume =	{5141},
  editor =	{Luca Benini and Ulrich Kremer and Christian W. Probst and Peter Schelkens},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.05141.8},
  URN =		{urn:nbn:de:0030-drops-3070},
  doi =		{10.4230/DagSemProc.05141.8},
  annote =	{Keywords: Wireless communication, channel coding, low power}
}

Filters

  • Authors
  • A
  • AbouGhazaleh, Nevine
  • Ayala, José Luis
  • B
  • Benini, Luca
  • C
  • Childers, Bruce
  • F
  • Franz, Michael
  • H
  • Hom, Jerry
  • K
  • Kremer, Ulrich
  • L
  • Lópes-Vallejo, Marisa
  • M
  • Melhem, Rami
  • Mossé, Daniel
  • Mühlberger, Andreas
  • N
  • Neffe, Ulrich
  • P
  • Probst, Christian W.
  • R
  • Rieger, Edgar
  • Rothbart, Klaus
  • S
  • Schelkens, Peter
  • Steger, Christian
  • V
  • Venkatachalam, Vasanth
  • W
  • Wehn, Norbert
  • Weiss, Reinhold

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