Predictably and Efficiently Integrating COTS Cache Coherence in Real-Time Systems

Authors Mohamed Hossam, Mohamed Hassan



PDF
Thumbnail PDF

File

LIPIcs.ECRTS.2022.17.pdf
  • Filesize: 1.62 MB
  • 23 pages

Document Identifiers

Author Details

Mohamed Hossam
  • McMaster University, Hamilton, Canada
Mohamed Hassan
  • McMaster University, Hamilton, Canada

Cite AsGet BibTex

Mohamed Hossam and Mohamed Hassan. Predictably and Efficiently Integrating COTS Cache Coherence in Real-Time Systems. In 34th Euromicro Conference on Real-Time Systems (ECRTS 2022). Leibniz International Proceedings in Informatics (LIPIcs), Volume 231, pp. 17:1-17:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2022)
https://doi.org/10.4230/LIPIcs.ECRTS.2022.17

Abstract

The adoption of multi-core platforms in embedded real-time systems mandates predictable system components. Such components must guarantee the satisfaction of the timing constraints of various applications running on the system. One of the components that can break the system predictability is cache coherence, which ensures the correctness of shared data. This paper proposes a solution towards the enablement of predictable cache coherent real-time systems. The solution uses existing COTS coherence protocols and proposes a methodology to integrate them with legacy real-time arbiters without imposing any required modification to either of them. Doing so, the paper also works as an exploratory study of the integration of various coherence protocols with various predictable arbitration schemes leading to a total of 12 different architecture configurations. Evaluation against four state-of-the-art predictable coherence solutions as well as COTS-based solutions show that the proposed approach achieves the tightest existing latency bounds among predictable solutions with minimal performance degradation over the COTS ones.

Subject Classification

ACM Subject Classification
  • Computer systems organization → Real-time systems
  • Computer systems organization → Real-time system architecture
  • Computer systems organization → Multicore architectures
Keywords
  • Coherence
  • Shared Data
  • Caches
  • Multi-Core
  • Real-Time
  • Memory

Metrics

  • Access Statistics
  • Total Accesses (updated on a weekly basis)
    0
    PDF Downloads

References

  1. ARM. ARM CoreLink CCI-550 Cache Coherent Interconnect, Technical Reference Manual, 2015. URL: https://static.docs.arm.com/100282/0001/corelink_cci550_cache_coherent_interconnect_technical_reference_manual_100282_0001_01_en.pdf.
  2. ARM. Arm Cortex-A53 MPCore Processor Technical Reference Manual r0p4, 2016. URL: https://developer.arm.com/documentation/ddi0500/j/Level-2-Memory-System/Snoop-Control-Unit.
  3. ARM. Arm Cortex-A9 MPCore Technical Reference Manual r4p1, 2016. URL: https://developer.arm.com/documentation/100486/0401/snoop-control-unit.
  4. ARM. ARM Cortex-R82, Technical Reference Manual, 2021. URL: https://developer.arm.com/documentation/101548/0002/?lang=en.
  5. Ayoosh Bansal, Jayati Singh, Yifan Hao, Jen-Yang Wen, Renato Mancuso, and Marco Caccamo. Cache where you want! reconciling predictability and coherent caching. arXiv preprint, 2019. URL: http://arxiv.org/abs/1909.05349.
  6. Daniel Casini, Alessandro Biondi, Giorgiomaria Cicero, and Giorgio Buttazzo. Latency analysis of i/o virtualization techniques in hypervisor-based real-time systems. In 2021 IEEE 27th Real-Time and Embedded Technology and Applications Symposium (RTAS), pages 306-319. IEEE, 2021. Google Scholar
  7. Chun Chang. A Deep Dive on the QorIQ T2080 Processor, NXP, 2014. Google Scholar
  8. M. Chisholm, N. Kim, B. C. Ward, N. Otterness, J. H. Anderson, and F. D. Smith. Reconciling the tension between hardware isolation and data sharing in mixed-criticality, multicore systems. In IEEE Real-Time Systems Symposium (RTSS), 2016. Google Scholar
  9. David Kruckemyer Craig Forrest. Arteris Ncore™ Cache Coherent Interconnect, Technology Overview, 2006. Google Scholar
  10. Danlu Guo, Mohamed Hassan, Rodolfo Pellizzoni, and Hiren Patel. A comparative study of predictable dram controllers. ACM Transactions on Embedded Computing Systems (TECS), 17(2):1-23, 2018. Google Scholar
  11. Arne Hamann, Dakshina Dasari, Simon Kramer, Michael Pressler, and Falk Wurst. Communication centric design in complex automotive embedded systems. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik, 2017. Google Scholar
  12. Damien Hardy, Thomas Piquet, and Isabelle Puaut. Using bypass to tighten wcet estimates for multi-core processors with shared instruction caches. In 2009 30th IEEE Real-Time Systems Symposium, pages 68-77. IEEE, 2009. Google Scholar
  13. Mohamed Hassan. On the off-chip memory latency of real-time systems: Is ddr dram really the best option? In 2018 IEEE Real-Time Systems Symposium (RTSS), pages 495-505. IEEE, 2018. Google Scholar
  14. Mohamed Hassan. Discriminative coherence: Balancing performance and latency bounds in data-sharing multi-core real-time systems. In 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020). Schloss Dagstuhl-Leibniz-Zentrum für Informatik, 2020. Google Scholar
  15. Mohamed Hassan, Anirudh M Kaushik, and Hiren Patel. Predictable cache coherence for multi-core real-time systems. In 2017 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pages 235-246. IEEE, 2017. Google Scholar
  16. Mohamed Hassan and Rodolfo Pellizzoni. Bounding dram interference in cots heterogeneous mpsocs for mixed criticality systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(11):2323-2336, 2018. Google Scholar
  17. Salah Hessien and Mohamed Hassan. The best of all worlds: Improving predictability at the performance of conventional coherence with no protocol modifications. In 2020 IEEE Real-Time Systems Symposium (RTSS), pages 218-230. IEEE, 2020. Google Scholar
  18. Anirudh Mohan Kaushik, Mohamed Hassan, and Hiren Patel. Designing predictable cache coherence protocols for multi-core real-time systems. IEEE Transactions on Computers, 2020. Google Scholar
  19. Anirudh Mohan Kaushik and Hiren Patel. A systematic approach to achieving tight worst-case latency and high-performance under predictable cache coherence. In 2021 IEEE 27th Real-Time and Embedded Technology and Applications Symposium (RTAS), pages 105-117. IEEE, 2021. Google Scholar
  20. Anirudh Mohan Kaushik, Paulos Tegegn, Zhuanhao Wu, and Hiren Patel. Carp: A data communication mechanism for multi-core mixed-criticality systems. In 2019 IEEE Real-Time Systems Symposium (RTSS), pages 419-432. IEEE, 2019. Google Scholar
  21. Benjamin Lesage, Damien Hardy, and Isabelle Puaut. Shared data caches conflicts reduction for wcet computation in multi-core architectures. In 18th International Conference on Real-Time and Network Systems, page 2283, 2010. Google Scholar
  22. MILO MK MARTIN, MARK D HILL, and DANIEL J SORIN. Why on-chip cache coherence is here to stay. Communications of ACM, 2012. Google Scholar
  23. Vijay Nagarajan, Daniel J Sorin, Mark D Hill, and David A Wood. A primer on memory consistency and cache coherence. Synthesis Lectures on Computer Architecture, 15(1):1-294, 2020. Google Scholar
  24. Fong Pong and Michel Dubois. A new approach for the verification of cache coherence protocols. IEEE Transactions on Parallel and Distributed Systems, 6(8):773-787, 1995. Google Scholar
  25. J. A. Poovey, T. M. Conte, M. Levy, and S. Gal-On. A benchmark characterization of the EEMBC benchmark suite. IEEE Micro, 29(5):18-29, September 2009. URL: https://doi.org/10.1109/MM.2009.74.
  26. Christos Sakalis, Carl Leonardsson, Stefanos Kaxiras, and Alberto Ros. Splash-3: A properly synchronized benchmark suite for contemporary research. In 2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pages 101-111. IEEE, 2016. Google Scholar
  27. Nivedita Sritharan, Anirudh Kaushik, Mohamed Hassan, and Hiren Patel. Enabling predictable, simultaneous and coherent data sharing in mixed criticality systems. In 2019 IEEE Real-Time Systems Symposium (RTSS), pages 433-445. IEEE, 2019. Google Scholar
  28. Mohamed Younis and Mohamed Aboutabl. Communication handling in integrated modular avionics, October 3 2002. US Patent App. 09/821,601. Google Scholar
Questions / Remarks / Feedback
X

Feedback for Dagstuhl Publishing


Thanks for your feedback!

Feedback submitted

Could not send message

Please try again later or send an E-mail