A VLSI Circuit Model Accounting for Wire Delay

Authors Ce Jin, R. Ryan Williams , Nathaniel Young



PDF
Thumbnail PDF

File

LIPIcs.ITCS.2024.66.pdf
  • Filesize: 0.82 MB
  • 22 pages

Document Identifiers

Author Details

Ce Jin
  • MIT, Cambridge, MA, USA
R. Ryan Williams
  • MIT, Cambridge, MA, USA
Nathaniel Young
  • Unaffiliated, San Jose, CA, USA

Acknowledgements

N.Y. thanks John Wawrzynek, his M.S. advisor, for excellent support on initial work on this topic, as well as Grace Dinh, Jonathan Greene, and Adrian Fan for useful conversations. C.J. and R.W. thank the Ethereum Foundation, in particular Justin Drake and Dankrad Feist, for highlighting various real-world computing issues that this work attempts to address. We all thank Avishay Tal for bringing us together to work on this topic.

Cite As Get BibTex

Ce Jin, R. Ryan Williams, and Nathaniel Young. A VLSI Circuit Model Accounting for Wire Delay. In 15th Innovations in Theoretical Computer Science Conference (ITCS 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 287, pp. 66:1-66:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024) https://doi.org/10.4230/LIPIcs.ITCS.2024.66

Abstract

Given the need for ever higher performance, and the failure of CPUs to keep providing single-threaded performance gains, engineers are increasingly turning to highly-parallel custom VLSI chips to implement expensive computations. In VLSI design, the gates and wires of a logical circuit are placed on a 2-dimensional chip with a small number of layers. Traditional VLSI models use gate delay to measure the time complexity of the chip, ignoring the lengths of wires. However, as technology has advanced, wire delay is no longer negligible; it has become an important measure in the design of VLSI chips [Markov, Nature (2014)].
Motivated by this situation, we define and study a model for VLSI chips, called wire-delay VLSI, which takes wire delay into account, going beyond an earlier model of Chazelle and Monier [JACM 1985].  
- We prove nearly tight upper bounds and lower bounds (up to logarithmic factors) on the time delay of this chip model for several basic problems. For example, And, Or and Parity require Θ(n^{1/3}) delay, while Addition and Multiplication require ̃ Θ(n^{1/2}) delay, and Triangle Detection on (dense) n-node graphs requires ̃ Θ(n) delay. Interestingly, when we allow input bits to be read twice, the delay for Addition can be improved to Θ(n^{1/3}). 
- We also show that proving significantly higher lower bounds in our wire-delay VLSI model would imply breakthrough results in circuit lower bounds. Motivated by this barrier, we also study conditional lower bounds on the delay of chips based on the Orthogonal Vectors Hypothesis from fine-grained complexity.

Subject Classification

ACM Subject Classification
  • Theory of computation → Models of computation
Keywords
  • circuit complexity
  • systolic arrays
  • VLSI
  • wire delay

Metrics

  • Access Statistics
  • Total Accesses (updated on a weekly basis)
    0
    PDF Downloads

References

  1. Amir Abboud, Arturs Backurs, and Virginia Williams. Tight hardness results for LCS and other sequence similarity measures. In Proceedings of IEEE FOCS, pages 59-78, October 2015. URL: https://doi.org/10.1109/FOCS.2015.14.
  2. Amir Abboud, R. Ryan Williams, and Huacheng Yu. More applications of the polynomial method to algorithm design. In Proceedings of ACM-SIAM SODA, pages 218-230. SIAM, 2015. URL: https://doi.org/10.1137/1.9781611973730.17.
  3. Noga Alon, Raphael Yuster, and Uri Zwick. Finding and counting given length cycles. Algorithmica, 17(3):209-223, 1997. URL: https://doi.org/10.1007/BF02523189.
  4. Arturs Backurs and Piotr Indyk. Edit distance cannot be computed in strongly subquadratic time (unless SETH is false). SIAM J. Comput., 47(3):1087-1097, 2018. URL: https://doi.org/10.1137/15M1053128.
  5. Richard P. Brent and H. T. Kung. The area-time complexity of binary multiplication. J. ACM, 28(3):521-534, 1981. URL: https://doi.org/10.1145/322261.322269.
  6. Karl Bringmann and Marvin Kunnemann. Quadratic conditional lower bounds for string problems and dynamic time warping. In Proceedings of IEEE FOCS, pages 79-97, October 2015. URL: https://doi.org/10.1109/FOCS.2015.15.
  7. Timothy M. Chan and R. Ryan Williams. Deterministic APSP, orthogonal vectors, and more: Quickly derandomizing Razborov-Smolensky. ACM Trans. Algorithms, 17(1):2:1-2:14, 2021. URL: https://doi.org/10.1145/3402926.
  8. Bernard Chazelle and Louis Monier. A model of computation for VLSI with related complexity results. In Proceedings of ACM STOC, pages 318-325. ACM, 1981. URL: https://doi.org/10.1145/800076.802485.
  9. Bernard Chazelle and Louis Monier. Unbounded hardware is equivalent to deterministic turing machines. Theor. Comput. Sci., 24:123-130, 1983. URL: https://doi.org/10.1016/0304-3975(83)90044-0.
  10. Bernard Chazelle and Louis Monier. A model of computation for VLSI with related complexity results. J. ACM, 32(3):573-588, 1985. URL: https://doi.org/10.1145/3828.3834.
  11. David C. Fisher. Your favorite parallel algorithms might not be as fast as you think. IEEE Transactions on Computers, 37(02):211-213, 1988. Google Scholar
  12. H. James Hoover, Maria M. Klawe, and Nicholas Pippenger. Bounding fan-out in logical networks. J. ACM, 31(1):13-18, 1984. URL: https://doi.org/10.1145/2422.322412.
  13. Ce Jin, Ryan Williams, and Nathaniel Young. A VLSI circuit model accounting for wire delay. Electron. Colloquium Comput. Complex., TR23-186, 2023. URL: https://eccc.weizmann.ac.il/report/2023/186/.
  14. Hongshin Jun, Jinhee Cho, Kangseol Lee, Ho-Young Son, Kwiwook Kim, Hanho Jin, and Keith Kim. Hbm (high bandwidth memory) dram technology and architecture. In 2017 IEEE International Memory Workshop (IMW), pages 1-4, 2017. URL: https://doi.org/10.1109/IMW.2017.7939084.
  15. Thomas Lengauer. VLSI theory. In Algorithms and Complexity, pages 835-868. Elsevier, 1990. Google Scholar
  16. Igor L. Markov. Limits on fundamental limits to computation. Nature, 512(7513):147-154, 2014. Google Scholar
  17. Kurt Mehlhorn and Franco P. Preparata. Area-time optimal VLSI integer multiplier with minimum computation time. Inf. Control., 58(1-3):137-156, 1983. URL: https://doi.org/10.1016/S0019-9958(83)80061-8.
  18. Christos H. Papadimitriou and Michael Sipser. Communication complexity. J. Comput. Syst. Sci., 28(2):260-269, 1984. URL: https://doi.org/10.1016/0022-0000(84)90069-2.
  19. Franco P. Preparata. A mesh-connected area-time optimal VLSI multiplier of large integers. IEEE Trans. Computers, 32(2):194-198, 1983. URL: https://doi.org/10.1109/TC.1983.1676203.
  20. Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. Digital integrated circuits- A design perspective. Prentice Hall, 2ed edition, 2004. Google Scholar
  21. Liam Roditty and Virginia Vassilevska Williams. Fast approximation algorithms for the diameter and radius of sparse graphs. In Proceedings of ACM STOC, pages 515-524. ACM, 2013. URL: https://doi.org/10.1145/2488608.2488673.
  22. Gerald B. Rosenberger. Simultaneous carry adder, December 27 1960. US Patent 2,966,305. Google Scholar
  23. John E Savage. Models of computation, volume 136. Addison-Wesley Reading, MA, 1998. Google Scholar
  24. Arnold Schönhage and Volker Strassen. Schnelle Multiplikation großer Zahlen [Fast multiplication of large numbers]. Computing, 7(3-4):281-292, 1971. URL: https://doi.org/10.1007/BF02242355.
  25. Rupesh S Shelar and Marek Patyra. Impact of local interconnects on timing and power in a high performance microprocessor. In Proceedings of the 19th international symposium on Physical design, pages 145-152, 2010. Google Scholar
  26. Clark David Thompson. A complexity theory for VLSI. Carnegie Mellon University, 1980. Google Scholar
  27. Jeffrey D Ullman. Computational Aspects of VLSI. Computer Science Press, 1984. Google Scholar
  28. Leslie G. Valiant and Gordon J. Brebner. Universal schemes for parallel communication. In Proceedings of ACM STOC, pages 263-277. ACM, 1981. URL: https://doi.org/10.1145/800076.802479.
  29. Virginia Vassilevska Williams. On some fine-grained questions in algorithms and complexity. In Proceedings of the International Congress of Mathematicians, pages 3447-3487. World Scientific, 2018. Google Scholar
  30. Ryan Williams. A new algorithm for optimal 2-constraint satisfaction and its implications. Theor. Comput. Sci., 348(2-3):357-365, 2005. URL: https://doi.org/10.1016/j.tcs.2005.09.023.
  31. Nathaniel Young. An updated model of computation for VLSI and applications to FPGA implementation. Master’s thesis, EECS Department, University of California, Berkeley, May 2022. URL: http://www2.eecs.berkeley.edu/Pubs/TechRpts/2022/EECS-2022-108.html.
Questions / Remarks / Feedback
X

Feedback for Dagstuhl Publishing


Thanks for your feedback!

Feedback submitted

Could not send message

Please try again later or send an E-mail