- DOI: 10.4230/LITES-v001-i001-a002
- URN:
SystemC/TLM models, which are C++ programs, allow the simulation of embedded software before hardware low-level descriptions are available and are used as golden models for hardware verification. The verification of the SystemC/TLM models is an important issue since an error in the model can mislead the system designers or reveal an error in the specifications. An open-source simulator for SystemC/TLM is provided but there are no tools for formal verification.In order to apply model checking to a SystemC/TLM model, a semantics for standard C++ code and for specific SystemC/TLM features must be provided. The usual approach relies on the translation of the SystemC/TLM code into a formal language for which a model checker is available.We propose another approach that suppresses the error-prone translation effort. Given a SystemC/TLM program, the transitions are obtained by executing the original code using g++ and an extended SystemC library, and we ask the user to provide additional functions to store the current model state. These additional functions generally represent less than 20% of the size of the original model, and allow it to apply all CADP verification tools to the SystemC/TLM model itself.
@Article{helmstetter:LITES-v001-i001-a002, author = {Helmstetter, Claude}, title = {{TLM.open: a SystemC/TLM Frontend for the CADP Verification Toolbox}}, journal = {Leibniz Transactions on Embedded Systems}, pages = {02:1--02:18}, ISSN = {2199-2002}, year = {2014}, volume = {1}, number = {1}, publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik}, address = {Dagstuhl, Germany}, URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v001-i001-a002}, doi = {10.4230/LITES-v001-i001-a002}, annote = {Keywords: Model checking, Verification, Simulation, SystemC, Transactional modeling} }
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