H-MBR: Hypervisor-Level Memory Bandwidth Reservation for Mixed Criticality Systems

Authors Afonso Oliveira , Diogo Costa , Gonçalo Moreira , José Martins , Sandro Pinto



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Afonso Oliveira
  • Centro ALGORITMI / LASI, Universidade do Minho, Portugal
Diogo Costa
  • Centro ALGORITMI / LASI, Universidade do Minho, Portugal
Gonçalo Moreira
  • Centro ALGORITMI / LASI, Universidade do Minho, Portugal
José Martins
  • Centro ALGORITMI / LASI, Universidade do Minho, Portugal
Sandro Pinto
  • Centro ALGORITMI / LASI, Universidade do Minho, Portugal

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Afonso Oliveira, Diogo Costa, Gonçalo Moreira, José Martins, and Sandro Pinto. H-MBR: Hypervisor-Level Memory Bandwidth Reservation for Mixed Criticality Systems. In Sixth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2025). Open Access Series in Informatics (OASIcs), Volume 128, pp. 4:1-4:15, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2025) https://doi.org/10.4230/OASIcs.NG-RES.2025.4

Abstract

Recent advancements in fields such as automotive and aerospace have driven a growing demand for robust computational resources. Applications that were once designed for basic Microcontroller Units (MCUs) are now deployed on highly heterogeneous System-on-Chip (SoC) platforms. While these platforms deliver the necessary computational performance, they also present challenges related to resource sharing and predictability. These challenges are particularly pronounced when consolidating safety-critical and non-safety-critical systems, the so-called Mixed-Criticality Systems (MCS) to adhere to strict Size, Weight, Power, and Cost (SWaP-C) requirements. MCS consolidation on shared platforms requires stringent spatial and temporal isolation to comply with functional safety standards (e.g., ISO 26262). Virtualization, mainly leveraged by hypervisors, is a key technology that ensures spatial isolation across multiple OSes and applications; however ensuring temporal isolation remains challenging due to contention on shared resources, such as main memory, caches, and system buses, which impacts real-time performance and predictability. To mitigate this problem, several strategies (e.g., cache coloring and memory bandwidth reservation) have been proposed. Although cache coloring is typically implemented on state-of-the-art hypervisors, memory bandwidth reservation approaches are commonly implemented at the Linux kernel level or rely on dedicated hardware and typically do not consider the concept of Virtual Machines that can run different OSes. To fill the gap between current memory bandwidth reservation solutions and the deployment of MCSs that operate on a hypervisor, this work introduces H-MBR, an open-source VM-centric memory bandwidth reservation mechanism. H-MBR features (i) VM-centric bandwidth reservation, (ii) OS and platform agnosticism, and (iii) reduced overhead. Empirical results evidenced no overhead on non-regulated workloads, and negligible overhead (<1%) for regulated workloads for regulation periods of 2 µs or higher.

Subject Classification

ACM Subject Classification
  • Computer systems organization → Real-time system specification
  • Computer systems organization → Embedded software
Keywords
  • Virtualization
  • Multi-core Interference
  • Mixed-Criticality Systems
  • Arm
  • Memory Bandwidth Reservation

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