Volume
OASIcs, Volume 128
Sixth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2025)
-
Part of:
Series:
Open Access Series in Informatics (OASIcs)
Conference: Workshop on Next Generation Real-Time Embedded Systems (NG-RES)
Event
NG-RES 2025, January 20, 2025, Barcelona, SpainEditors
Publication Details
- published at: 2025-03-25
- Publisher: Schloss Dagstuhl – Leibniz-Zentrum für Informatik
- ISBN: 978-3-95977-366-9
- DBLP: db/conf/hipeac/ngres2025
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Document
Complete Volume
OASIcs, Volume 128, NG-RES 2025, Complete Volume
Abstract
OASIcs, Volume 128, NG-RES 2025, Complete Volume
Cite as
Sixth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2025). Open Access Series in Informatics (OASIcs), Volume 128, pp. 1-82, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2025)
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@Proceedings{yomsi_et_al:OASIcs.NG-RES.2025,
title = {{OASIcs, Volume 128, NG-RES 2025, Complete Volume}},
booktitle = {Sixth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2025)},
pages = {1--82},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-366-9},
ISSN = {2190-6807},
year = {2025},
volume = {128},
editor = {Yomsi, Patrick Meumeu and Wildermann, Stefan},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2025},
URN = {urn:nbn:de:0030-drops-230023},
doi = {10.4230/OASIcs.NG-RES.2025},
annote = {Keywords: OASIcs, Volume 128, NG-RES 2025, Complete Volume}
}
Document
Front Matter
Front Matter, Table of Contents, Preface, Conference Organization
Abstract
Front Matter, Table of Contents, Preface, Conference Organization
Cite as
Sixth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2025). Open Access Series in Informatics (OASIcs), Volume 128, pp. 0:i-0:x, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2025)
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@InProceedings{yomsi_et_al:OASIcs.NG-RES.2025.0,
author = {Yomsi, Patrick Meumeu and Wildermann, Stefan},
title = {{Front Matter, Table of Contents, Preface, Conference Organization}},
booktitle = {Sixth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2025)},
pages = {0:i--0:x},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-366-9},
ISSN = {2190-6807},
year = {2025},
volume = {128},
editor = {Yomsi, Patrick Meumeu and Wildermann, Stefan},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2025.0},
URN = {urn:nbn:de:0030-drops-230012},
doi = {10.4230/OASIcs.NG-RES.2025.0},
annote = {Keywords: Front Matter, Table of Contents, Preface, Conference Organization}
}
Document
Programming Time-Predictable Processors with Lingua Franca
Abstract
Precision-timed (PRET) machines are an alternative to modern processors that provide precise control over the timing of software execution. This paper describes a platform for developing predictable real-time embedded systems that pair PRET machines with Lingua Franca (LF), a recent reactor-based coordination language with temporal semantics. Specifically, we port LF to FlexPRET, a PRET machine with flexible hardware thread scheduling. We evaluate single-threaded LF with a tight control loop style application on four embedded platforms, including the FlexPRET. The results reveal the underlying platform’s timing variability and how LF plus FlexPRET can remedy this timing variability. Finally, we compare single-threaded to multithreaded LF, again concerning timing. The four embedded platforms used are FlexPRET (bare-metal), RP2040 (bare-metal), nRF52 (with Zephyr), and Raspberry Pi 3b+ (with Linux). Our results indicate that FlexPRET with LF is attractive when precise timing is essential.
Cite as
Magnus Mæhlum, Erling Rennemo Jellum, Shaokai Lin, Marten Lohstroh, Martin Schoeberl, Sverre Hendseth, and Edward A. Lee. Programming Time-Predictable Processors with Lingua Franca. In Sixth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2025). Open Access Series in Informatics (OASIcs), Volume 128, pp. 1:1-1:13, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2025)
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@InProceedings{maehlum_et_al:OASIcs.NG-RES.2025.1,
author = {M{\ae}hlum, Magnus and Jellum, Erling Rennemo and Lin, Shaokai and Lohstroh, Marten and Schoeberl, Martin and Hendseth, Sverre and Lee, Edward A.},
title = {{Programming Time-Predictable Processors with Lingua Franca}},
booktitle = {Sixth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2025)},
pages = {1:1--1:13},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-366-9},
ISSN = {2190-6807},
year = {2025},
volume = {128},
editor = {Yomsi, Patrick Meumeu and Wildermann, Stefan},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2025.1},
URN = {urn:nbn:de:0030-drops-229876},
doi = {10.4230/OASIcs.NG-RES.2025.1},
annote = {Keywords: Real-time systems, time-predictable architecture, embedded system, coordination language}
}
Document
Low-Latency Real-Time Applications on Heterogeneous MPSoCs
Abstract
Heterogeneous Multi-Processor Systems-on-Chip (MPSoCs) that combine multiple, heterogeneous processing units are becoming increasingly popular for a wide range of applications, including industrial applications, where complex real-time applications can benefit from the performance and flexibility they offer.
However, deploying real-time applications with low latency requirements across multiple processing units on such MPSoCs remains a challenging problem, particularly when communication between processors is required on a time-critical path. Existing solutions generally rely on the presence of at least one full-featured, general-purpose operating system on the device, and do not cater to the requirements of distributed, low-latency real-time applications.
In this paper, we investigate the performance, with a focus on latency, of different options for communication between CPUs, including inter-processor interrupts and shared memory communication via different memories, on the popular Xilinx Zynq UltraScale+ platform and propose a novel solution for communication between heterogeneous processing units that relies only on the availability of shared memory. Our solution is capable of achieving sub-microsecond latencies for signaling and the transfer of small amounts of data between processing units, making it suitable for deploying distributed, low-latency real-time applications.
Cite as
Nicolas Coppik, Pascal Becker, and Marcus Ritter. Low-Latency Real-Time Applications on Heterogeneous MPSoCs. In Sixth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2025). Open Access Series in Informatics (OASIcs), Volume 128, pp. 2:1-2:14, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2025)
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@InProceedings{coppik_et_al:OASIcs.NG-RES.2025.2,
author = {Coppik, Nicolas and Becker, Pascal and Ritter, Marcus},
title = {{Low-Latency Real-Time Applications on Heterogeneous MPSoCs}},
booktitle = {Sixth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2025)},
pages = {2:1--2:14},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-366-9},
ISSN = {2190-6807},
year = {2025},
volume = {128},
editor = {Yomsi, Patrick Meumeu and Wildermann, Stefan},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2025.2},
URN = {urn:nbn:de:0030-drops-229883},
doi = {10.4230/OASIcs.NG-RES.2025.2},
annote = {Keywords: real-time systems, heterogeneous systems, latency, inter-core communication}
}
Document
Co-Design of Systems-On-Chip for Sustainability
Abstract
This paper introduces a novel approach to the co-design of sustainable embedded systems through multi-objective design space exploration (DSE). We propose a two-phase methodology that optimizes both the multiprocessor system-on-chip (MPSoC) architecture and application mappings, considering sustainability, reliability, performance, and cost as optimization objectives of equal importance. Unlike existing approaches, our method thereby accounts for both operational and embodied emissions, providing a more comprehensive assessment of sustainability. The first phase employs intra-application DSEs to explore Pareto-optimal constraint graphs for each application. The second phase, an inter-application DSE, combines these results to explore sustainable target architectures and corresponding application mappings. Our approach incorporates detailed models for embodied emissions (scope 1 and scope 2), operational emissions, reliability, performance, and cost. The evaluation demonstrates that our sustainability-aware DSE is able to explore design spaces overlooked by traditional approaches, supported by superior results in four key objectives. This enables the development of more environmentally friendly embedded systems while still achieving high performance and reliability.
Cite as
Jan Spieck, Dominik Walter, Jan Waschkeit, and Jürgen Teich. Co-Design of Systems-On-Chip for Sustainability. In Sixth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2025). Open Access Series in Informatics (OASIcs), Volume 128, pp. 3:1-3:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2025)
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@InProceedings{spieck_et_al:OASIcs.NG-RES.2025.3,
author = {Spieck, Jan and Walter, Dominik and Waschkeit, Jan and Teich, J\"{u}rgen},
title = {{Co-Design of Systems-On-Chip for Sustainability}},
booktitle = {Sixth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2025)},
pages = {3:1--3:12},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-366-9},
ISSN = {2190-6807},
year = {2025},
volume = {128},
editor = {Yomsi, Patrick Meumeu and Wildermann, Stefan},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2025.3},
URN = {urn:nbn:de:0030-drops-229898},
doi = {10.4230/OASIcs.NG-RES.2025.3},
annote = {Keywords: System-on-Chip, Sustainability, Multi-objective Optimization, Design Space Exploration, Embedded Systems, Carbon Emissions}
}
Document
H-MBR: Hypervisor-Level Memory Bandwidth Reservation for Mixed Criticality Systems
Abstract
Recent advancements in fields such as automotive and aerospace have driven a growing demand for robust computational resources. Applications that were once designed for basic Microcontroller Units (MCUs) are now deployed on highly heterogeneous System-on-Chip (SoC) platforms. While these platforms deliver the necessary computational performance, they also present challenges related to resource sharing and predictability. These challenges are particularly pronounced when consolidating safety-critical and non-safety-critical systems, the so-called Mixed-Criticality Systems (MCS) to adhere to strict Size, Weight, Power, and Cost (SWaP-C) requirements. MCS consolidation on shared platforms requires stringent spatial and temporal isolation to comply with functional safety standards (e.g., ISO 26262). Virtualization, mainly leveraged by hypervisors, is a key technology that ensures spatial isolation across multiple OSes and applications; however ensuring temporal isolation remains challenging due to contention on shared resources, such as main memory, caches, and system buses, which impacts real-time performance and predictability. To mitigate this problem, several strategies (e.g., cache coloring and memory bandwidth reservation) have been proposed. Although cache coloring is typically implemented on state-of-the-art hypervisors, memory bandwidth reservation approaches are commonly implemented at the Linux kernel level or rely on dedicated hardware and typically do not consider the concept of Virtual Machines that can run different OSes. To fill the gap between current memory bandwidth reservation solutions and the deployment of MCSs that operate on a hypervisor, this work introduces H-MBR, an open-source VM-centric memory bandwidth reservation mechanism. H-MBR features (i) VM-centric bandwidth reservation, (ii) OS and platform agnosticism, and (iii) reduced overhead. Empirical results evidenced no overhead on non-regulated workloads, and negligible overhead (<1%) for regulated workloads for regulation periods of 2 µs or higher.
Cite as
Afonso Oliveira, Diogo Costa, Gonçalo Moreira, José Martins, and Sandro Pinto. H-MBR: Hypervisor-Level Memory Bandwidth Reservation for Mixed Criticality Systems. In Sixth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2025). Open Access Series in Informatics (OASIcs), Volume 128, pp. 4:1-4:15, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2025)
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@InProceedings{oliveira_et_al:OASIcs.NG-RES.2025.4,
author = {Oliveira, Afonso and Costa, Diogo and Moreira, Gon\c{c}alo and Martins, Jos\'{e} and Pinto, Sandro},
title = {{H-MBR: Hypervisor-Level Memory Bandwidth Reservation for Mixed Criticality Systems}},
booktitle = {Sixth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2025)},
pages = {4:1--4:15},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-366-9},
ISSN = {2190-6807},
year = {2025},
volume = {128},
editor = {Yomsi, Patrick Meumeu and Wildermann, Stefan},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2025.4},
URN = {urn:nbn:de:0030-drops-229905},
doi = {10.4230/OASIcs.NG-RES.2025.4},
annote = {Keywords: Virtualization, Multi-core Interference, Mixed-Criticality Systems, Arm, Memory Bandwidth Reservation}
}
Document
SP-IMPact: A Framework for Static Partitioning Interference Mitigation and Performance Analysis
Abstract
Modern embedded systems are evolving toward complex, heterogeneous architectures to accommodate increasingly demanding applications. Driven by industry SWAP-C (Size, Weight, Power, and Cost) constraints, this shift has led to the consolidation of multiple systems onto single hardware platforms. Static Partitioning Hypervisors (SPHs) offer a promising solution to partition hardware resources and provide spatial isolation between critical workloads. However, shared hardware resources like the Last-Level Cache (LLC) and system bus can introduce significant temporal interference between virtual machines (VMs), negatively impacting performance and predictability. Over the past decade, academia and industry have focused on developing interference mitigation techniques, such as cache partitioning and memory bandwidth reservation. Configuring these techniques, however, is complex and time-consuming. Cache partitioning requires careful balancing of cache sections across VMs, while memory bandwidth reservation requires tuning bandwidth budgets and periods. With numerous possible configurations, testing all combinations is impractical and often leads to suboptimal configurations. Moreover, there is a gap in understanding how these techniques interact, as their combined use can result in compounded or conflicting effects on system performance. Static analysis solutions that estimate worst-case execution times (WCET) and upper bounds on execution times provide some guidance for configuring interference mitigation techniques. While useful in identifying potential interference effects, these tools often fail to capture the full complexity of modern multi-core systems, as they typically focus on a limited set of shared resources and neglect other sources of contention, such as IOMMUs and interrupt controllers. To address these challenges, we introduce SP-IMPact, an open-source framework designed to analyze and guide the configuration of interference mitigation techniques, through the deployment of diverse VM configurations and setups, and assessment of hardware-level contention (leveraging SPHs). It supports two mitigation techniques: (i) cache coloring and (ii) memory bandwidth reservation, while also evaluating the interactions between these techniques and their cumulative impact on system performance. By providing insights on real hardware platforms, SP-IMPact helps to optimize the configuration of these techniques in mixed-criticality systems, ensuring both performance and predictability.
Cite as
Diogo Costa, Gonçalo Moreira, Afonso Oliveira, José Martins, and Sandro Pinto. SP-IMPact: A Framework for Static Partitioning Interference Mitigation and Performance Analysis. In Sixth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2025). Open Access Series in Informatics (OASIcs), Volume 128, pp. 5:1-5:15, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2025)
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@InProceedings{costa_et_al:OASIcs.NG-RES.2025.5,
author = {Costa, Diogo and Moreira, Gon\c{c}alo and Oliveira, Afonso and Martins, Jos\'{e} and Pinto, Sandro},
title = {{SP-IMPact: A Framework for Static Partitioning Interference Mitigation and Performance Analysis}},
booktitle = {Sixth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2025)},
pages = {5:1--5:15},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-366-9},
ISSN = {2190-6807},
year = {2025},
volume = {128},
editor = {Yomsi, Patrick Meumeu and Wildermann, Stefan},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2025.5},
URN = {urn:nbn:de:0030-drops-229911},
doi = {10.4230/OASIcs.NG-RES.2025.5},
annote = {Keywords: Virtualization, Contention, Multi-core Interference, Mixed-Criticality Systems, Arm}
}