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Adjacent LSTM-Based Page Scheduling for Hybrid DRAM/NVM Memory Systems

Authors Manolis Katsaragakis, Konstantinos Stavrakakis, Dimosthenis Masouros, Lazaros Papadopoulos, Dimitrios Soudris



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Author Details

Manolis Katsaragakis
  • Microprocessors and Digital Systems Laboratory, National Technical University of Athens, Greece
Konstantinos Stavrakakis
  • Microprocessors and Digital Systems Laboratory, National Technical University of Athens, Greece
Dimosthenis Masouros
  • Microprocessors and Digital Systems Laboratory, National Technical University of Athens, Greece
Lazaros Papadopoulos
  • Microprocessors and Digital Systems Laboratory, National Technical University of Athens, Greece
Dimitrios Soudris
  • Microprocessors and Digital Systems Laboratory, National Technical University of Athens, Greece

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Manolis Katsaragakis, Konstantinos Stavrakakis, Dimosthenis Masouros, Lazaros Papadopoulos, and Dimitrios Soudris. Adjacent LSTM-Based Page Scheduling for Hybrid DRAM/NVM Memory Systems. In 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023). Open Access Series in Informatics (OASIcs), Volume 107, pp. 7:1-7:12, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2023)
https://doi.org/10.4230/OASIcs.PARMA-DITAM.2023.7

Abstract

Recent advances in memory technologies have led to the rapid growth of hybrid systems that combine traditional DRAM and Non Volatile Memory (NVM) technologies, as the latter provide lower cost per byte, low leakage power and larger capacities than DRAM, while they can guarantee comparable access latency. Such kind of heterogeneous memory systems impose new challenges in terms of page placement and migration among the alternative technologies of the heterogeneous memory system. In this paper, we present a novel approach for efficient page placement on heterogeneous DRAM/NVM systems. We design an adjacent LSTM-based approach for page placement, which strongly relies on page accesses prediction, while sharing knowledge among pages with behavioral similarity. The proposed approach leads up to 65.5% optimized performance compared to existing approaches, while achieving near-optimal results and saving 20.2% energy consumption on average. Moreover, we propose a new page replacement policy, namely clustered-LRU, achieving up to 8.1% optimized performance, compared to the default Least Recently Used (LRU) policy.

Subject Classification

ACM Subject Classification
  • Computer systems organization → Heterogeneous (hybrid) systems
  • Hardware → Emerging tools and methodologies
Keywords
  • Page Placement
  • Long Short-Term Memory
  • LSTM
  • Prediction
  • NVM
  • DRAM

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References

  1. Christian Bienia, Sanjeev Kumar, Jaswinder Pal Singh, and Kai Li. The parsec benchmark suite: Characterization and architectural implications. In Proceedings of the 17th international conference on Parallel architectures and compilation techniques, pages 72-81, 2008. Google Scholar
  2. Wesley Brewer, Greg Behm, Alan Scheinine, Ben Parsons, Wesley Emeneker, and Robert P Trevino. Inference benchmarking on hpc systems. In 2020 IEEE High Performance Extreme Computing Conference (HPEC), pages 1-9. IEEE, 2020. Google Scholar
  3. Shuai Che, Michael Boyer, Jiayuan Meng, David Tarjan, Jeremy W Sheaffer, Sang-Ha Lee, and Kevin Skadron. Rodinia: A benchmark suite for heterogeneous computing. In 2009 IEEE international symposium on workload characterization (IISWC), pages 44-54. Ieee, 2009. Google Scholar
  4. Yu Chen, Ivy B Peng, Zhen Peng, Xu Liu, and Bin Ren. Atmem: Adaptive data placement in graph applications on heterogeneous memories. In Proceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization, pages 293-304, 2020. Google Scholar
  5. Thaleia Dimitra Doudali, Sergey Blagodurov, Abhinav Vishnu, Sudhanva Gurumurthi, and Ada Gavrilovska. Kleio: A hybrid memory page scheduler with machine intelligence. In Proceedings of the 28th International Symposium on High-Performance Parallel and Distributed Computing, pages 37-48, 2019. Google Scholar
  6. Zhuohui Duan, Haikun Liu, Xiaofei Liao, Hai Jin, Wenbin Jiang, and Yu Zhang. Hinuma: Numa-aware data placement and migration in hybrid memory systems. In 2019 IEEE 37th International Conference on Computer Design (ICCD), pages 367-375. IEEE, 2019. Google Scholar
  7. Subramanya R Dulloor, Amitabha Roy, Zheguang Zhao, Narayanan Sundaram, Nadathur Satish, Rajesh Sankaran, Jeff Jackson, and Karsten Schwan. Data tiering in heterogeneous memory systems. In Proceedings of the Eleventh European Conference on Computer Systems, pages 1-16, 2016. Google Scholar
  8. Milad Hashemi, Kevin Swersky, Jamie Smith, Grant Ayers, Heiner Litz, Jichuan Chang, Christos Kozyrakis, and Parthasarathy Ranganathan. Learning memory access patterns. In International Conference on Machine Learning, pages 1919-1928. PMLR, 2018. Google Scholar
  9. Ahmad Hassan, Dimitrios S Nikolopoulos, and Hans Vandierendonck. Fast and energy-efficient olap data management on hybrid main memory systems. IEEE Transactions on Computers, 68(11), 2019. Google Scholar
  10. Manolis Katsaragakis, Lazaros Papadopoulos, Christos Baloukas, and Dimitrios Soudris. Memory management methodology for application data structure refinement and placement on heterogeneous dram/nvm systems. In 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 748-753. IEEE, 2022. Google Scholar
  11. Manolis Katsaragakis, Lazaros Papadopoulos, Mario Konijnenburg, Francky Catthoor, and Dimitrios Soudris. Memory footprint optimization techniques for machine learning applications in embedded systems. In 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1-4. IEEE, 2020. Google Scholar
  12. Vamsee Reddy Kommareddy, Simon David Hammond, Clayton Hughes, Ahmad Samih, and Amro Awad. Page migration support for disaggregated non-volatile memories. In Proceedings of the International Symposium on Memory Systems, pages 417-427, 2019. Google Scholar
  13. Zhe Li and Mingyu Wu. Transparent and lightweight object placement for managed workloads atop hybrid memories. In Proceedings of the 18th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, pages 72-80, 2022. Google Scholar
  14. Felix Xiaozhu Lin and Xu Liu. Memif: Towards programming heterogeneous memory asynchronously. ACM SIGPLAN Notices, 51(4):369-383, 2016. Google Scholar
  15. Chi-Keung Luk, Robert Cohn, Robert Muth, Harish Patil, Artur Klauser, Geoff Lowney, Steven Wallace, Vijay Janapa Reddi, and Kim Hazelwood. Pin: building customized program analysis tools with dynamic instrumentation. Acm sigplan notices, 40(6):190-200, 2005. Google Scholar
  16. Mitesh R Meswani, Sergey Blagodurov, David Roberts, John Slice, Mike Ignatowski, and Gabriel H Loh. Heterogeneous memory architectures: A hw/sw approach for mixing die-stacked and off-package memories. In 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), pages 126-136. IEEE, 2015. Google Scholar
  17. Prashant J Nair, Dae-Hyun Kim, and Moinuddin K Qureshi. Archshield: Architectural framework for assisting dram scaling by tolerating high error rates. ACM SIGARCH Computer Architecture News, 41(3), 2013. Google Scholar
  18. Leeor Peled, Uri Weiser, and Yoav Etsion. A neural network prefetcher for arbitrary memory access patterns. ACM Transactions on Architecture and Code Optimization (TACO), 16(4):1-27, 2019. Google Scholar
  19. Ivy B Peng, Maya B Gokhale, and Eric W Green. System evaluation of the intel optane byte-addressable nvm. In Proceedings of the International Symposium on Memory Systems, pages 304-315, 2019. Google Scholar
  20. Yuan Zeng and Xiaochen Guo. Long short term memory based hardware prefetcher: a case study. In Proceedings of the International Symposium on Memory Systems, pages 305-311, 2017. Google Scholar
  21. Yiming Zhang, Jinyu Zhan, Junhuan Yang, Wei Jiang, Lin Li, and Yixin Li. Energy-aware page replacement for nvm based hybrid main memory system. In 2017 IEEE 23rd International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pages 1-6. IEEE, 2017. Google Scholar
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