Volume
OASIcs, Volume 107
14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)
Event
PARMA-DITAM 2023, January 17, 2023, Toulouse, FranceEditors
Publication Details
- published at: 2023-03-13
- Publisher: Schloss Dagstuhl – Leibniz-Zentrum für Informatik
- ISBN: 978-3-95977-269-3
- DBLP: db/conf/hipeac/parma2023
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Document
Complete Volume
OASIcs, Volume 107, PARMA-DITAM 2023, Complete Volume
Abstract
OASIcs, Volume 107, PARMA-DITAM 2023, Complete Volume
Cite as
14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023). Open Access Series in Informatics (OASIcs), Volume 107, pp. 1-98, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
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@Proceedings{bispo_et_al:OASIcs.PARMA-DITAM.2023,
title = {{OASIcs, Volume 107, PARMA-DITAM 2023, Complete Volume}},
booktitle = {14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)},
pages = {1--98},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-269-3},
ISSN = {2190-6807},
year = {2023},
volume = {107},
editor = {Bispo, Jo\~{a}o and Charles, Henri-Pierre and Cherubin, Stefano and Massari, Giuseppe},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2023},
URN = {urn:nbn:de:0030-drops-177193},
doi = {10.4230/OASIcs.PARMA-DITAM.2023},
annote = {Keywords: OASIcs, Volume 107, PARMA-DITAM 2023, Complete Volume}
}
Document
Front Matter
Front Matter, Table of Contents, Preface, Conference Organization
Abstract
Front Matter, Table of Contents, Preface, Conference Organization
Cite as
14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023). Open Access Series in Informatics (OASIcs), Volume 107, pp. 0:i-0:x, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
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@InProceedings{bispo_et_al:OASIcs.PARMA-DITAM.2023.0,
author = {Bispo, Jo\~{a}o and Charles, Henri-Pierre and Cherubin, Stefano and Massari, Giuseppe},
title = {{Front Matter, Table of Contents, Preface, Conference Organization}},
booktitle = {14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)},
pages = {0:i--0:x},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-269-3},
ISSN = {2190-6807},
year = {2023},
volume = {107},
editor = {Bispo, Jo\~{a}o and Charles, Henri-Pierre and Cherubin, Stefano and Massari, Giuseppe},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2023.0},
URN = {urn:nbn:de:0030-drops-177206},
doi = {10.4230/OASIcs.PARMA-DITAM.2023.0},
annote = {Keywords: Front Matter, Table of Contents, Preface, Conference Organization}
}
Document
Invited Paper
ByteNite: A New Business Model for Grid Computing (Invited Paper)
Abstract
Years and years of technological advancement have paved the way to cloud computing towards Industry 4.0, making it possible for a wide range of cloud solutions to become a reality, bringing innovation and efficiency to business processes and changing our lifestyles. With the benefit of hindsight in a fully digitalized era, have we ever wondered where does cloud computing come from? Furthermore, as the on-premise commercial model shifted to cloud computing with the advent of the internet, what will the increase in worldwide connectivity and the rise of 5G turn the cloud model into? This article describes in a model for a new commercial grid computing implementation, called "ByteNite". We open the paper with the state of the art of the distributed computing models, including an overview of cloud and grid computing, their commonalities and history, and how they are topical in today’s world. We build the foundations of our work through a key insight that triggers powerful implications in connection with the current technologies. We address the new proposed model through a description of the system, its overall functioning, the underlying business concepts and the innovative value proposition. We finally then dive into its architecture and workflow design, delineating its structure and key features, and the chronological phases of its operation.
Cite as
Fabio Caironi and Niccolò Andrea Castelli. ByteNite: A New Business Model for Grid Computing (Invited Paper). In 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023). Open Access Series in Informatics (OASIcs), Volume 107, pp. 1:1-1:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
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@InProceedings{caironi_et_al:OASIcs.PARMA-DITAM.2023.1,
author = {Caironi, Fabio and Castelli, Niccol\`{o} Andrea},
title = {{ByteNite: A New Business Model for Grid Computing}},
booktitle = {14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)},
pages = {1:1--1:12},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-269-3},
ISSN = {2190-6807},
year = {2023},
volume = {107},
editor = {Bispo, Jo\~{a}o and Charles, Henri-Pierre and Cherubin, Stefano and Massari, Giuseppe},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2023.1},
URN = {urn:nbn:de:0030-drops-177210},
doi = {10.4230/OASIcs.PARMA-DITAM.2023.1},
annote = {Keywords: Grid Computing, Cloud Computing, Distributed Applications, High-Throughput Computing, dApps, Utility Computing}
}
Document
Invited Paper
Challenges and Opportunities in C/C++ Source-To-Source Compilation (Invited Paper)
Abstract
The C/C++ compilation stack (Intermediate Representations (IR), compilation passes and backends) is encumbered by a steep learning curve, which we believe can be lowered by complementing it with approaches such as source-to-source compilation. Source-to-source compilation is a technology that is widely used and quite mature in certain programming environments, such as JavaScript, but that faces a low adoption rate in others. In the particular case of C and C++ some of the identified factors include the high complexity of the languages, increased difficulty in building and maintaining C/C++ parsers, or limitations on using source code as an intermediate representation. Additionally, new technologies such as Multi-Level Intermediate Representation (MLIR) have appeared as potential competitors to source-to-source compilers at this level.
In this paper, we present what we have identified as current challenges of source-to-source compilation of C and C++, as well as what we consider to be opportunities and possible directions forward. We also present several examples, implemented on top of the Clava source-to-source compiler, that use some of these ideas and techniques to raise the abstraction level of compiler research on complex compiled languages such as C or C++. The examples include automatic parallelization of for loops, high-level synthesis optimisation, hardware/software partitioning with run-time decisions, and automatic insertion of inline assembly for fast prototyping of custom instructions.
Cite as
João Bispo, Nuno Paulino, and Luís Miguel Sousa. Challenges and Opportunities in C/C++ Source-To-Source Compilation (Invited Paper). In 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023). Open Access Series in Informatics (OASIcs), Volume 107, pp. 2:1-2:15, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
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@InProceedings{bispo_et_al:OASIcs.PARMA-DITAM.2023.2,
author = {Bispo, Jo\~{a}o and Paulino, Nuno and Sousa, Lu{\'\i}s Miguel},
title = {{Challenges and Opportunities in C/C++ Source-To-Source Compilation}},
booktitle = {14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)},
pages = {2:1--2:15},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-269-3},
ISSN = {2190-6807},
year = {2023},
volume = {107},
editor = {Bispo, Jo\~{a}o and Charles, Henri-Pierre and Cherubin, Stefano and Massari, Giuseppe},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2023.2},
URN = {urn:nbn:de:0030-drops-177225},
doi = {10.4230/OASIcs.PARMA-DITAM.2023.2},
annote = {Keywords: Source-to-source, compilation, transpilers, C/C++, code transformation}
}
Document
Invited Paper
RUST-Encoded Stream Ciphers on a RISC-V Parallel Ultra-Low-Power Processor (Invited Paper)
Abstract
Nowadays, the development of security applications is a relevant topic in the Internet of Things (IoT) and cyber-physical systems (CPS) fields. Different embedded architectures have been adopted in these areas, but the RISC-V parallel ultra-low-power (PULP) architecture stands out as a particularly efficient system. However, it has never been proposed to enable cryptography. In the context of video stream security, stream ciphers enable an efficient solution to ensure data privacy, and the exploitation of the PULP multi-core accelerator cluster paves the way to an efficient implementation of these ciphers. In this paper, we exploit the capability of the PULP architecture coupled with the code safety provided by the RUST programming language to design and implement an efficient stream encryption algorithm. We present a wrapper system between the development libraries of a PULP platform enabling the secure execution of a verified RUST-written implementation of ChaCha20 and AES-CTR, targeting a microdrones based video surveillance system. Experimental tests have resulted in an encryption efficiency of ChaCha20 of 2.3 cycles per Byte (cB), placing the resulting implementation at the state-of-the-art, in direct competition with higher-class architectures like Apple M1 (2.0 cB).
Cite as
Francesco Barchi, Giacomo Pasini, Emanuele Parisi, Giuseppe Tagliavini, Andrea Bartolini, and Andrea Acquaviva. RUST-Encoded Stream Ciphers on a RISC-V Parallel Ultra-Low-Power Processor (Invited Paper). In 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023). Open Access Series in Informatics (OASIcs), Volume 107, pp. 3:1-3:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
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@InProceedings{barchi_et_al:OASIcs.PARMA-DITAM.2023.3,
author = {Barchi, Francesco and Pasini, Giacomo and Parisi, Emanuele and Tagliavini, Giuseppe and Bartolini, Andrea and Acquaviva, Andrea},
title = {{RUST-Encoded Stream Ciphers on a RISC-V Parallel Ultra-Low-Power Processor}},
booktitle = {14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)},
pages = {3:1--3:12},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-269-3},
ISSN = {2190-6807},
year = {2023},
volume = {107},
editor = {Bispo, Jo\~{a}o and Charles, Henri-Pierre and Cherubin, Stefano and Massari, Giuseppe},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2023.3},
URN = {urn:nbn:de:0030-drops-177232},
doi = {10.4230/OASIcs.PARMA-DITAM.2023.3},
annote = {Keywords: Parallel Low-Power Embedded Systems, Rust, RISC-V, Stream Cipher}
}
Document
An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE
Abstract
NIST is conducting a process for the standardization of post-quantum cryptosystems, i.e., cryptosystems that are resistant to attacks by both traditional and quantum computers and that can thus substitute the traditional public-key cryptography solutions which are expected to be broken by quantum computers in the next decades. This manuscript provides an overview and a comparison of the existing state-of-the-art implementations of the BIKE QC-MDPC code-based post-quantum KEM, a candidate in NIST’s PQC standardization process. We consider both software, hardware, and mixed hardware-software implementations and evaluate their performance and, for hardware ones, their resource utilization.
Cite as
Andrea Galimberti, Gabriele Montanaro, William Fornaciari, and Davide Zoni. An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE. In 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023). Open Access Series in Informatics (OASIcs), Volume 107, pp. 4:1-4:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
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@InProceedings{galimberti_et_al:OASIcs.PARMA-DITAM.2023.4,
author = {Galimberti, Andrea and Montanaro, Gabriele and Fornaciari, William and Zoni, Davide},
title = {{An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE}},
booktitle = {14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)},
pages = {4:1--4:12},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-269-3},
ISSN = {2190-6807},
year = {2023},
volume = {107},
editor = {Bispo, Jo\~{a}o and Charles, Henri-Pierre and Cherubin, Stefano and Massari, Giuseppe},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2023.4},
URN = {urn:nbn:de:0030-drops-177249},
doi = {10.4230/OASIcs.PARMA-DITAM.2023.4},
annote = {Keywords: Post-quantum cryptography, QC-MDPC code-based cryptography, BIKE, software execution, hardware acceleration, hardware-software co-design, performance evaluation}
}
Document
MonTM: Monitoring-Based Thermal Management for Mixed-Criticality Systems
Abstract
With a rapidly growing functionality of embedded real-time applications, it becomes inevitable to integrate tasks of different safety integrity levels on one many-core processor leading to a large-scale mixed-criticality system. In this process, it is not sufficient to only isolate shared architectural resources, as different tasks executing on different cores also possibly interfere via the many-core processor’s thermal management. This can possibly lead to best-effort tasks causing deadline violations for safety-critical tasks. In order to prevent such a scenario, we propose a monitoring-based hardware extension that communicates imminent thermal violations between cores via a lightweight interconnect. Building on this infrastructure, we propose a thermal strategy such that best-effort tasks can be throttled in favor of safety-critical tasks. Furthermore, assigning static voltage/frequency (V/f) levels to each safety-critical task based on their worst-case execution time may result in unnecessary high V/f levels when the actual execution finishes faster. To free the otherwise wasted thermal resources, our solution monitors the progress of safety-critical tasks to detect slack and safely reduce their V/f levels. This increases the thermal headroom for best-effort tasks, boosting their performance. In our evaluation, we demonstrate our approach on an 80-core processor to show that it satisfies the thermal and deadline requirements, and simultaneously reduces the run-time of best-effort tasks by up to 45% compared to the state of the art.
Cite as
Marcel Mettler, Martin Rapp, Heba Khdr, Daniel Mueller-Gritschneder, Jörg Henkel, and Ulf Schlichtmann. MonTM: Monitoring-Based Thermal Management for Mixed-Criticality Systems. In 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023). Open Access Series in Informatics (OASIcs), Volume 107, pp. 5:1-5:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
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@InProceedings{mettler_et_al:OASIcs.PARMA-DITAM.2023.5,
author = {Mettler, Marcel and Rapp, Martin and Khdr, Heba and Mueller-Gritschneder, Daniel and Henkel, J\"{o}rg and Schlichtmann, Ulf},
title = {{MonTM: Monitoring-Based Thermal Management for Mixed-Criticality Systems}},
booktitle = {14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)},
pages = {5:1--5:12},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-269-3},
ISSN = {2190-6807},
year = {2023},
volume = {107},
editor = {Bispo, Jo\~{a}o and Charles, Henri-Pierre and Cherubin, Stefano and Massari, Giuseppe},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2023.5},
URN = {urn:nbn:de:0030-drops-177250},
doi = {10.4230/OASIcs.PARMA-DITAM.2023.5},
annote = {Keywords: Dynamic thermal management, mixed-criticality, monitoring}
}
Document
Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments
Abstract
Since its introduction in 2017, the Posit™ format for representing real numbers has attracted a lot of interest, as an alternative to IEEE 754 floating point representation. Several hardware implementations of arithmetic operations between posit numbers have also been proposed in recent years. In this work, we analyze the dynamic power consumption of the Full Posit Processing Unit (FPPU) recently developed at the University of Pisa. Experimental results show that we can model the dynamic power consumption of the FPPU with an acceptable approximation error from 2.84% (32-bit FPPU) to 7.32% (8-bit FPPU). Furthermore, from the synthesis of the power monitoring unit alongside the FPPU we demonstrate that the additional power module has an area cost that goes from ∼5% (32-bit FPPU) to ∼30% (8-bit FPPU) of the total unit area occupation.
Cite as
Michele Piccoli, Davide Zoni, William Fornaciari, Giuseppe Massari, Marco Cococcioni, Federico Rossi, Sergio Saponara, and Emanuele Ruffaldi. Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments. In 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023). Open Access Series in Informatics (OASIcs), Volume 107, pp. 6:1-6:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
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@InProceedings{piccoli_et_al:OASIcs.PARMA-DITAM.2023.6,
author = {Piccoli, Michele and Zoni, Davide and Fornaciari, William and Massari, Giuseppe and Cococcioni, Marco and Rossi, Federico and Saponara, Sergio and Ruffaldi, Emanuele},
title = {{Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments}},
booktitle = {14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)},
pages = {6:1--6:11},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-269-3},
ISSN = {2190-6807},
year = {2023},
volume = {107},
editor = {Bispo, Jo\~{a}o and Charles, Henri-Pierre and Cherubin, Stefano and Massari, Giuseppe},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2023.6},
URN = {urn:nbn:de:0030-drops-177268},
doi = {10.4230/OASIcs.PARMA-DITAM.2023.6},
annote = {Keywords: power estimation, computer arithmetic, posit numbers}
}
Document
Adjacent LSTM-Based Page Scheduling for Hybrid DRAM/NVM Memory Systems
Abstract
Recent advances in memory technologies have led to the rapid growth of hybrid systems that combine traditional DRAM and Non Volatile Memory (NVM) technologies, as the latter provide lower cost per byte, low leakage power and larger capacities than DRAM, while they can guarantee comparable access latency. Such kind of heterogeneous memory systems impose new challenges in terms of page placement and migration among the alternative technologies of the heterogeneous memory system. In this paper, we present a novel approach for efficient page placement on heterogeneous DRAM/NVM systems. We design an adjacent LSTM-based approach for page placement, which strongly relies on page accesses prediction, while sharing knowledge among pages with behavioral similarity. The proposed approach leads up to 65.5% optimized performance compared to existing approaches, while achieving near-optimal results and saving 20.2% energy consumption on average. Moreover, we propose a new page replacement policy, namely clustered-LRU, achieving up to 8.1% optimized performance, compared to the default Least Recently Used (LRU) policy.
Cite as
Manolis Katsaragakis, Konstantinos Stavrakakis, Dimosthenis Masouros, Lazaros Papadopoulos, and Dimitrios Soudris. Adjacent LSTM-Based Page Scheduling for Hybrid DRAM/NVM Memory Systems. In 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023). Open Access Series in Informatics (OASIcs), Volume 107, pp. 7:1-7:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
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@InProceedings{katsaragakis_et_al:OASIcs.PARMA-DITAM.2023.7,
author = {Katsaragakis, Manolis and Stavrakakis, Konstantinos and Masouros, Dimosthenis and Papadopoulos, Lazaros and Soudris, Dimitrios},
title = {{Adjacent LSTM-Based Page Scheduling for Hybrid DRAM/NVM Memory Systems}},
booktitle = {14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)},
pages = {7:1--7:12},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-269-3},
ISSN = {2190-6807},
year = {2023},
volume = {107},
editor = {Bispo, Jo\~{a}o and Charles, Henri-Pierre and Cherubin, Stefano and Massari, Giuseppe},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2023.7},
URN = {urn:nbn:de:0030-drops-177278},
doi = {10.4230/OASIcs.PARMA-DITAM.2023.7},
annote = {Keywords: Page Placement, Long Short-Term Memory, LSTM, Prediction, NVM, DRAM}
}