OASIcs.WCET.2005.813.pdf
- Filesize: 285 kB
- 4 pages
Document
Analysis of Memory Latencies in Multi-Processor Systems
Authors
-
Part of:
Volume:
5th International Workshop on Worst-Case Execution Time Analysis (WCET'05) (WCET 2005)
Series: Open Access Series in Informatics (OASIcs)
Conference: Workshop on Worst-Case Execution Time Analysis (WCET) - License:
Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported license
- Publication Date: 2007-03-29
Cite AsGet BibTex
Jan Stachulat, Simon Schliecker, Matthias Ivers, and Rolf Ernst. Analysis of Memory Latencies in Multi-Processor Systems. In 5th International Workshop on Worst-Case Execution Time Analysis (WCET'05). Open Access Series in Informatics (OASIcs), Volume 1, pp. 33-36, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2007)
https://doi.org/10.4230/OASIcs.WCET.2005.813
https://doi.org/10.4230/OASIcs.WCET.2005.813
Abstract
Predicting timing behavior is key to efficient embedded
real-time system design and verification. Current approaches
to determine end-to-end latencies in parallel heterogeneous
architectures focus on performance analysis either
on task or system level. Especially memory accesses,
basic operations of embedded application, cannot be accurately
captured on a single level alone: While task level
methods simplify system behavior, system level methods
simplify task behavior. Both perspectives lead to overly pessimistic
estimations.
To tackle these complex interactions we integrate task
and system level analysis. Each analysis level is provided
with the necessary data to allow precise computations,
while adequate abstraction prevents high time complexity.
Keywords
- Multi-processor Performance Analysis
- Memory Access Latency
- Worst Case Execution Time
Metrics
- Access Statistics
-
Total Accesses (updated on a weekly basis)
0PDF Downloads