Software-enforced Interconnect Arbitration for COTS Multicores

Authors Marco Ziccardi, Alessandro Cornaglia, Enrico Mezzetti, Tullio Vardanega

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Marco Ziccardi
Alessandro Cornaglia
Enrico Mezzetti
Tullio Vardanega

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Marco Ziccardi, Alessandro Cornaglia, Enrico Mezzetti, and Tullio Vardanega. Software-enforced Interconnect Arbitration for COTS Multicores. In 15th International Workshop on Worst-Case Execution Time Analysis (WCET 2015). Open Access Series in Informatics (OASIcs), Volume 47, pp. 11-20, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2015)


The advent of multicore processors complicates timing analysis owing to the need to account for the interference between cores accessing shared resources, which is not always easy to characterize in a safe and tight way. Solutions have been proposed that take two distinct but complementary directions: on the one hand, complex analysis techniques have been developed to provide safe and tight bounds to contention; on the other hand, sophisticated arbitration policies (hardware or software) have been proposed to limit or control inter-core interference. In this paper we propose a software-based TDMA-like arbitration of accesses to a shared interconnect (e.g. a bus) that prevents inter-core interference. A more flexible arbitration scheme is also proposed to reserve more bandwidth to selected cores while still avoiding contention. A proof-of-concept implementation on an AURIX TC277TU processor shows that our approach can apply to COTS processors, thus not relying on dedicated hardware arbiters, while introducing little overhead.
  • Multicore
  • Resource Arbitration
  • Interference
  • Mixed-Criticality


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