Issue
Leibniz Transactions on Embedded Systems, Volume 1, Issue 2
LITES, Volume 1, Issue 2
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Volume:
LITES, Volume 1
Journal: Leibniz Transactions on Embedded Systems (LITES)
Publication Details
- published at: 2014-09-12
- Publisher: Schloss Dagstuhl – Leibniz-Zentrum für Informatik
- DBLP: db/journals/lites/lites1
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Document
Complete Issue
LITES, Volume 1, Issue 2
Abstract
LITES, Volume 1, Issue 2
Cite as
LITES, Volume 1, Issue 2, pp. 1-67, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2014)
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@Article{LITES-v001-i002,
title = {{LITES, Volume 1, Issue 2}},
journal = {Leibniz Transactions on Embedded Systems},
pages = {1--67},
ISSN = {2199-2002},
year = {2014},
volume = {1},
number = {2},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v001-i002},
doi = {10.4230/LITES-v001-i002},
annote = {Keywords: LITES, Volume 1, Issue 2}
}
Document
Blocking Optimality in Distributed Real-Time Locking Protocols
Abstract
Lower and upper bounds on the maximum priority inversion blocking (pi-blocking) that is generally unavoidable in distributed multiprocessor real-time locking protocols (where resources may be accessed only from specific synchronization processors) are established. Prior work on suspension-based shared-memory multiprocessor locking protocols (which require resources to be accessible from all processors) has established asymptotically tight bounds of Ω(m) and Ω(n) maximum pi-blocking under suspension-oblivious and suspension-aware analysis, respectively, where m denotes the total number of processors and n denotes the number of tasks. In this paper, it is shown that, in the case of distributed semaphore protocols, there exist two different task allocation scenarios that give rise to distinct lower bounds. In the case of co-hosted task allocation, where application tasks may also be assigned to synchronization processors (i.e., processors hosting critical sections), Ω(Φ · n) maximum pi-blocking is unavoidable for some tasks under any locking protocol under both suspension-aware and suspension-oblivious schedulability analysis, where Φ denotes the ratio of the maximum response time to the shortest period. In contrast, in the case of disjoint task allocation (i.e., if application tasks may not be assigned to synchronization processors), only Ω(m) and Ω(n) maximum pi-blocking is fundamentally unavoidable under suspension-oblivious and suspension-aware analysis, respectively, as in the shared-memory case. These bounds are shown to be asymptotically tight with the construction of two new distributed real-time locking protocols that ensure O(m) and O(n) maximum pi-blocking under suspension-oblivious and suspension-aware analysis, respectively.
Cite as
Björn Bernhard Brandenburg. Blocking Optimality in Distributed Real-Time Locking Protocols. In LITES, Volume 1, Issue 2 (2014). Leibniz Transactions on Embedded Systems, Volume 1, Issue 2, pp. 01:1-01:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2014)
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@Article{brandenburg:LITES-v001-i002-a001,
author = {Brandenburg, Bj\"{o}rn Bernhard},
title = {{Blocking Optimality in Distributed Real-Time Locking Protocols}},
journal = {Leibniz Transactions on Embedded Systems},
pages = {01:1--01:22},
ISSN = {2199-2002},
year = {2014},
volume = {1},
number = {2},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v001-i002-a001},
URN = {urn:nbn:de:0030-drops-192479},
doi = {10.4230/LITES-v001-i002-a001},
annote = {Keywords: Distributed multiprocessor real-time systems, Real-time locking, Priority inversion, Blocking optimality}
}
Document
Computation Offloading for Frame-Based Real-Time Tasks under Given Server Response Time Guarantees
Abstract
Computation offloading has been adopted to improve the performance of embedded systems by offloading the computation of some tasks, especially computation-intensive tasks, to servers or clouds. This paper explores computation offloading for real-time tasks in embedded systems, provided given response time guarantees from the servers, to decide which tasks should be offloaded to get the results in time. We consider frame-based real-time tasks with the same period and relative deadline. When the execution order of the tasks is given, the problem can be solved in linear time. However, when the execution order is not specified, we prove that the problem is NP-complete. We develop a pseudo-polynomial-time algorithm for deriving feasible schedules, if they exist. An approximation scheme is also developed to trade the error made from the algorithm and the complexity. Our algorithms are extended to minimize the period/relative deadline of the tasks for performance maximization. The algorithms are evaluated with a case study for a surveillance system and synthesized benchmarks.
Cite as
Anas S. M. Toma and Jian-Jia Chen. Computation Offloading for Frame-Based Real-Time Tasks under Given Server Response Time Guarantees. In LITES, Volume 1, Issue 2 (2014). Leibniz Transactions on Embedded Systems, Volume 1, Issue 2, pp. 02:1-02:21, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2014)
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@Article{toma_et_al:LITES-v001-i002-a002,
author = {Toma, Anas S. M. and Chen, Jian-Jia},
title = {{Computation Offloading for Frame-Based Real-Time Tasks under Given Server Response Time Guarantees}},
journal = {Leibniz Transactions on Embedded Systems},
pages = {02:1--02:21},
ISSN = {2199-2002},
year = {2014},
volume = {1},
number = {2},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v001-i002-a002},
URN = {urn:nbn:de:0030-drops-192489},
doi = {10.4230/LITES-v001-i002-a002},
annote = {Keywords: Computation offloading, Task scheduling, Real-time systems}
}
Document
Implementing Mixed-criticality Systems Upon a Preemptive Varying-speed Processor
Abstract
A mixed criticality (MC) workload consists of components of varying degrees of importance (or "criticalities"); the more critical components typically need to have their correctness validated to greater levels of assurance than the less critical ones. The problem of executing such a MC workload upon a preemptive processor whose effective speed may vary during run-time, in a manner that is not completely known prior to run-time, is considered.Such a processor is modeled as being characterized by several execution speeds: a normal speed and several levels of degraded speed. Under normal circumstances it will execute at or above its normal speed; conditions during run-time may cause it to execute slower. It is desired that all components of the MC workload execute correctly under normal circumstances. If the processor speed degrades, it should nevertheless remain the case that the more critical components execute correctly (although the less critical ones need not do so).In this work, we derive an optimal algorithm for scheduling MC workloads upon such platforms; achieving optimality does not require that the processor be able to monitor its own run-time speed. For the sub-case of the general problem where there are only two criticality levels defined, we additionally provide an implementation that is asymptotically optimal in terms of run-time efficiency.
Cite as
Zhishan Guo and Sanjoy K. Baruah. Implementing Mixed-criticality Systems Upon a Preemptive Varying-speed Processor. In LITES, Volume 1, Issue 2 (2014). Leibniz Transactions on Embedded Systems, Volume 1, Issue 2, pp. 03:1-03:19, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2014)
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@Article{guo_et_al:LITES-v001-i002-a003,
author = {Guo, Zhishan and Baruah, Sanjoy K.},
title = {{Implementing Mixed-criticality Systems Upon a Preemptive Varying-speed Processor}},
journal = {Leibniz Transactions on Embedded Systems},
pages = {03:1--03:19},
ISSN = {2199-2002},
year = {2014},
volume = {1},
number = {2},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v001-i002-a003},
URN = {urn:nbn:de:0030-drops-192498},
doi = {10.4230/LITES-v001-i002-a003},
annote = {Keywords: Mixed criticalities, Varying-speed processor, Preemptive uniprocessor scheduling, }
}