DARTS.6.1.4.pdf
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Document
Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact)
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Part of:
Issue:
Special Issue of the 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020)
Volume: DARTS, Volume 6 (ECOOP 2020)
Conference: Euromicro Conference on Real-Time Systems (ECRTS)
Journal: Dagstuhl Artifacts Series (DARTS) - License:
Creative Commons Attribution 3.0 Unported license
- Publication Date: 2020-06-30
Artifact Description
Document Identifiers
Cite AsGet BibTex
Francesco Restuccia, Marco Pagani, Alessandro Biondi, Mauro Marinoni, and Giorgio Buttazzo. Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact). In Special Issue of the 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020). Dagstuhl Artifacts Series (DARTS), Volume 6, Issue 1, pp. 4:1-4:3, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2020)
https://doi.org/10.4230/DARTS.6.1.4
https://doi.org/10.4230/DARTS.6.1.4
Artifact
DARTS-6-1-4-artifact-0228fd08ccc8ebd51b3e6cb1eabdb486.tgz
(Filesize: 11 kB)
Abstract
This artifact provides the means for reproducing the experiments presented in the paper "Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoC". In particular, it provides the means and describes how to replicate the experimental study that has been carried out to evaluate the proposed analysis with synthetic workloads.
Subject Classification
ACM Subject Classification
- Hardware → Interconnect
- Hardware → Hardware accelerators
Keywords
- Heterogeneous computing
- Predictable hardware acceleration
- FPGA SoCs
- Multi-Master architectures
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