Wear Leveling Revisited

Authors Taku Onodera, Tetsuo Shibuya



PDF
Thumbnail PDF

File

LIPIcs.ISAAC.2020.65.pdf
  • Filesize: 0.54 MB
  • 17 pages

Document Identifiers

Author Details

Taku Onodera
  • Department of Computer Science, University of Helsinki, Finland
Tetsuo Shibuya
  • Human Genome Center, Institute of Medical Science, The University of Tokyo, Japan

Acknowledgements

The first author thanks Keisuke Goto for encouragement to publish the result.

Cite AsGet BibTex

Taku Onodera and Tetsuo Shibuya. Wear Leveling Revisited. In 31st International Symposium on Algorithms and Computation (ISAAC 2020). Leibniz International Proceedings in Informatics (LIPIcs), Volume 181, pp. 65:1-65:17, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2020)
https://doi.org/10.4230/LIPIcs.ISAAC.2020.65

Abstract

Wear leveling - a technology designed to balance the write counts among memory cells regardless of the requested accesses - is vital in prolonging the lifetime of certain computer memory devices, especially the type of next-generation non-volatile memory, known as phase change memory (PCM). Although researchers have been working extensively on wear leveling, almost all existing studies mainly focus on the practical aspects and lack rigorous mathematical analyses. The lack of theory is particularly problematic for security-critical applications. We address this issue by revisiting wear leveling from a theoretical perspective. First, we completely determine the problem parameter regime for which Security Refresh - one of the most well-known existing wear leveling schemes for PCM - works effectively by providing a positive result and a matching negative result. In particular, Security Refresh is not competitive for the practically relevant regime of large-scale memory. Then, we propose a novel scheme that achieves better lifetime, time/space overhead, and wear-free space for the relevant regime not covered by Security Refresh. Unlike existing studies, we give rigorous theoretical lifetime analyses, which is necessary to assess and control the security risk.

Subject Classification

ACM Subject Classification
  • Theory of computation → Data structures design and analysis
  • Hardware → Memory and dense storage
  • Security and privacy → Security in hardware
Keywords
  • Wear leveling
  • Randomized algorithm
  • Non-volatile memory

Metrics

  • Access Statistics
  • Total Accesses (updated on a weekly basis)
    0
    PDF Downloads

References

  1. Marjan Asadinia, Majid Jalili, and Hamid Sarbazi-Azad. Bless: A simple and efficient scheme for prolonging pcm lifetime. In Proceedings of the 53rd Annual Design Automation Conference, DAC '16, pages 93:1-93:6, New York, NY, USA, 2016. ACM. URL: https://doi.org/10.1145/2897937.2897993.
  2. Amir Ban. Wear leveling of static areas in flash memory, May 2004. US Patent 6,732,221. Google Scholar
  3. Avraham Ben-Aroya and Sivan Toledo. Competitive analysis of flash memory algorithms. ACM Trans. Algorithms, 7(2):23:1-23:37, March 2011. URL: https://doi.org/10.1145/1921659.1921669.
  4. Stéphane Boucheron, Gábor Lugosi, and Pascal Massart. Concentration inequalities: A nonasymptotic theory of independence. Oxford university press, 2013. Google Scholar
  5. Jalil Boukhobza, Stéphane Rubini, Renhai Chen, and Zili Shao. Emerging nvm: A survey on architectural integration and research challenges. ACM Trans. Des. Autom. Electron. Syst., 23(2):14:1-14:32, November 2017. URL: https://doi.org/10.1145/3131848.
  6. Chi-Hao Chen, Pi-Cheng Hsiu, Tei-Wei Kuo, Chia-Lin Yang, and Cheng-Yuan Michael Wang. Age-based pcm wear leveling with nearly zero search cost. In Proceedings of the 49th Annual Design Automation Conference, DAC '12, pages 453-458, New York, NY, USA, 2012. ACM. URL: https://doi.org/10.1145/2228360.2228439.
  7. Jianbo Dong, Lei Zhang, Yinhe Han, Ying Wang, and Xiaowei Li. Wear rate leveling: Lifetime enhancement of pram with endurance variation. In Proceedings of the 48th Design Automation Conference, DAC '11, pages 972-977, New York, NY, USA, 2011. ACM. URL: https://doi.org/10.1145/2024724.2024939.
  8. David Eppstein, Michael T. Goodrich, Michael Mitzenmacher, and Paweł Pszona. Wear minimization for cuckoo hashing: How not to throw a lot of eggs into one basket. In Joachim Gudmundsson and Jyrki Katajainen, editors, Proceedings of the 13th International Symposium on Experimental Algorithms, pages 162-173, Cham, 2014. Springer International Publishing. Google Scholar
  9. Jingtong Hu, Mimi Xie, Chen Pan, Chun Jason Xue, Qingfeng Zhuge, and Edwin Hsing-Mean Sha. Low overhead software wear leveling for hybrid pcm + dram main memory on embedded systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(4):654-663, April 2015. URL: https://doi.org/10.1109/TVLSI.2014.2321571.
  10. Mohammad Reza Jokar, Mohammad Arjomand, and Hamid Sarbazi-Azad. Sequoia: A high-endurance nvm-based cache architecture. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(3):954-967, March 2016. URL: https://doi.org/10.1109/TVLSI.2015.2420954.
  11. Qingyue Liu and Peter Varman. Ouroboros wear leveling for nvram using hierarchical block migration. ACM Trans. Storage, 13(4):30:1-30:31, November 2017. URL: https://doi.org/10.1145/3139530.
  12. Karl M. J. Lofgren, Robert D. Norman, Gregory B. Thelin, and Anil Gupta. Wear leveling techniques for flash eeprom systems, May 2001. US Patent 6,230,233. Google Scholar
  13. Kurt Mehlhorn and Peter Sanders. Algorithms and Data Structures: The Basic Toolbox. Springer Publishing Company, Incorporated, 1st edition, 2010. Google Scholar
  14. Sung Kyu Park, Min Kyu Maeng, Ki-Woong Park, and Kyu Ho Park. Adaptive wear-leveling algorithm for pram main memory with a dram buffer. ACM Trans. Embed. Comput. Syst., 13(4):88:1-88:25, March 2014. URL: https://doi.org/10.1145/2558427.
  15. Moinuddin K. Qureshi, Michele Franceschini, Vijayalakshmi Srinivasan, Luis Lastras, Bulent Abali, and John Karidis. Enhancing lifetime and security of pcm-based main memory with start-gap wear leveling. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 42, pages 14-23, New York, NY, USA, 2009. ACM. URL: https://doi.org/10.1145/1669112.1669117.
  16. Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, and Jude A. Rivers. Scalable high performance main memory system using phase-change memory technology. SIGARCH Comput. Archit. News, 37(3):24-33, June 2009. URL: https://doi.org/10.1145/1555815.1555760.
  17. Nak Hee Seong, Dong Hyuk Woo, and Hsien-Hsin Lee. Security refresh: Protecting phase-change memory against malicious wear out. IEEE Micro, 31(1):119-127, January 2011. URL: https://doi.org/10.1109/MM.2010.101.
  18. André Seznec. Towards Phase Change Memory as a Secure Main Memory. Research Report RR-7088, INRIA, 2009. URL: https://hal.inria.fr/inria-00430010.
  19. André Seznec. A phase change memory as a secure main memory. IEEE Computer Architecture Letters, 9(1):5-8, January 2010. URL: https://doi.org/10.1109/L-CA.2010.2.
  20. Guangyp Sun, Dimin Niu, Jin Ouyang, and Yuan Xie. A frequent-value based pram memory architecture. In 16th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 211-216, January 2011. URL: https://doi.org/10.1109/ASPDAC.2011.5722186.
  21. Gang Wu, Huxing Zhang, Yaozu Dong, and Jingtong Hu. Car: Securing pcm main memory system with cache address remapping. In 18th IEEE International Conference on Parallel and Distributed Systems, pages 628-635, December 2012. URL: https://doi.org/10.1109/ICPADS.2012.90.
  22. Hongliang Yu and Yuyang Du. Increasing endurance and security of phase-change memory with multi-way wear-leveling. IEEE Transactions on Computers, 63(5):1157-1168, May 2014. URL: https://doi.org/10.1109/TC.2012.292.
  23. Joosung Yun, Sunggu Lee, and Sungjoo Yoo. Dynamic wear leveling for phase-change memories with endurance variations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(9):1604-1615, September 2015. URL: https://doi.org/10.1109/TVLSI.2014.2350073.
  24. Mengying Zhao, Liang Shi, Chengmo Yang, and Chun Jason Xue. Leveling to the last mile: Near-zero-cost bit level wear leveling for pcm-based main memory. In Proceedings of the 32nd IEEE International Conference on Computer Design (ICCD), pages 16-21, October 2014. URL: https://doi.org/10.1109/ICCD.2014.6974656.
  25. Pengfei Zuo and Yu Hua. Secpm: a secure and persistent memory system for non-volatile memory. In 10th USENIX Workshop on Hot Topics in Storage and File Systems (HotStorage 18), Boston, MA, 2018. USENIX Association. URL: https://www.usenix.org/conference/hotstorage18/presentation/zuo.
Questions / Remarks / Feedback
X

Feedback for Dagstuhl Publishing


Thanks for your feedback!

Feedback submitted

Could not send message

Please try again later or send an E-mail