Timing Anomalies Reloaded

Gebhard, Gernot

doi:10.4230/OASIcs.WCET.2010.1

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Timing Anomalies Reloaded

Author Gernot Gebhard

Part of: Volume: 10th International Workshop on Worst-Case Execution Time Analysis (WCET 2010)
Part of: Series: Open Access Series in Informatics (OASIcs)
Part of: Conference: Workshop on Worst-Case Execution Time Analysis (WCET)
License: Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported license
Publication Date: 2010-11-26

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Document Identifiers

DOI: 10.4230/OASIcs.WCET.2010.1
URN: urn:nbn:de:0030-drops-28201

Subject Classification

Keywords

Timing Anomalies
Domino Effects
MRU Replacement Policy
LEON2

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Abstract

Computing tight WCET bounds in the presence of timing anomalies - found in almost any modern hardware architecture - is a major challenge of timing analysis.
In this paper, we renew the discussion about timing anomalies, demonstrating that even simple hardware architectures are prone to timing anomalies.  We furthermore complete the list of timing-anomalous cache replacement policies, proving that the most-recently-used replacement policy (MRU) also exhibits a domino effect.

Cite As Get BibTex

Gernot Gebhard. Timing Anomalies Reloaded. In 10th International Workshop on Worst-Case Execution Time Analysis (WCET 2010). Open Access Series in Informatics (OASIcs), Volume 15, pp. 1-10, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010) https://doi.org/10.4230/OASIcs.WCET.2010.1

Author Details

Gernot Gebhard

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