Creative Commons Attribution 3.0 Unported license
In the last decade there has been a steady uptrend in the popularity of embedded multi-core platforms. This represents a turning point in the theory and implementation of real-time systems. From a real-time standpoint, however, the extensive sharing of hardware resources (e.g. caches, DRAM subsystem, I/O channels) represents a major source of unpredictability. Budget-based memory regulation (throttling) has been extensively studied to enforce a strict partitioning of the DRAM subsystem’s bandwidth. The common approach to analyze a task under memory bandwidth regulation is to consider the budget of the core where the task is executing, and assume the worst-case about the remaining cores' budgets. In this work, we propose a novel analysis strategy to derive the WCET of a task under memory bandwidth regulation that takes into account the exact distribution of memory budgets to cores. In this sense, the proposed analysis represents a generalization of approaches that consider (i) even budget distribution across cores; and (ii) uneven but unknown (except for the core under analysis) budget assignment. By exploiting the additional piece of information, we show that it is possible to derive a more accurate WCET estimation. Our evaluations highlight that the proposed technique can reduce overestimation by 30% in average, and up to 60%, compared to the state of the art.
@InProceedings{mancuso_et_al:LIPIcs.ECRTS.2017.3,
author = {Mancuso, Renato and Pellizzoni, Rodolfo and Tokcan, Neriman and Caccamo, Marco},
title = {{WCET Derivation under Single Core Equivalence with Explicit Memory Budget Assignment}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {3:1--3:23},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.3},
URN = {urn:nbn:de:0030-drops-71684},
doi = {10.4230/LIPIcs.ECRTS.2017.3},
annote = {Keywords: real-time multicore, WCET, single-core equivalence, DRAM management, certification}
}