Volume
LIPIcs, Volume 76
29th Euromicro Conference on Real-Time Systems (ECRTS 2017)
-
Part of:
Series:
Leibniz International Proceedings in Informatics (LIPIcs)
Conference: Euromicro Conference on Real-Time Systems (ECRTS)
Event
ECRTS 2017, June 27-30, 2017, Dubrovnik, CroatiaEditor
Publication Details
- published at: 2017-06-23
- Publisher: Schloss Dagstuhl – Leibniz-Zentrum für Informatik
- ISBN: 978-3-95977-037-8
- DBLP: db/conf/ecrts/ecrts2017
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Document
Complete Volume
LIPIcs, Volume 76, ECRTS'17, Complete Volume
Abstract
LIPIcs, Volume 76, ECRTS'17, Complete Volume
Cite as
29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@Proceedings{bertogna:LIPIcs.ECRTS.2017,
title = {{LIPIcs, Volume 76, ECRTS'17, Complete Volume}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017},
URN = {urn:nbn:de:0030-drops-73648},
doi = {10.4230/LIPIcs.ECRTS.2017},
annote = {Keywords: Real-Time and Embedded Systems, Performance of Systems, Processors, Scheduling, Real-Time Systems and Embedded Systems and Embedded Systems}
}
Document
Front Matter
Front Matter, Table of Contents, Preface, Committees, List of Authors
Abstract
Front Matter, Table of Contents, Preface, Committees, List of Authors
Cite as
29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 0:i-0:xvi, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{bertogna:LIPIcs.ECRTS.2017.0,
author = {Bertogna, Marko},
title = {{Front Matter, Table of Contents, Preface, Committees, List of Authors}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {0:i--0:xvi},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.0},
URN = {urn:nbn:de:0030-drops-71495},
doi = {10.4230/LIPIcs.ECRTS.2017.0},
annote = {Keywords: Front Matter, Table of Contents, Preface, Committees, List of Authors}
}
Document
Bus-Aware Static Instruction SPM Allocation for Multicore Hard Real-Time Systems
Abstract
Over the past years, multicore systems emerged into the domain of hard real-time systems. These systems introduce common buses and shared memories which heavily influence the timing behavior. We show that existing WCET optimizations may lead to suboptimal results when applied to multicore setups. Additionally we provide both a genetic and a precise Integer Linear Programming (ILP)-based static instruction scratchpad memory allocation optimization which are capable of exploiting multicore properties, resulting in a WCET reduction of 26% in average compared with a bus-unaware optimization. Furthermore, we show that our ILP-based optimization's average runtime is distinctively lower in comparison to the genetic approach. Although limiting the number of tasks per core to one and partially exploiting private instruction SPMs, we cover the most crucial elements of a multicore setup: the interconnection and shared resources.
Cite as
Dominic Oehlert, Arno Luppold, and Heiko Falk. Bus-Aware Static Instruction SPM Allocation for Multicore Hard Real-Time Systems. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 1:1-1:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{oehlert_et_al:LIPIcs.ECRTS.2017.1,
author = {Oehlert, Dominic and Luppold, Arno and Falk, Heiko},
title = {{Bus-Aware Static Instruction SPM Allocation for Multicore Hard Real-Time Systems}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {1:1--1:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.1},
URN = {urn:nbn:de:0030-drops-71604},
doi = {10.4230/LIPIcs.ECRTS.2017.1},
annote = {Keywords: Compiler, Optimization, WCET, Real-Time, Multicore}
}
Document
Contention-Aware Dynamic Memory Bandwidth Isolation with Predictability in COTS Multicores: An Avionics Case Study
Abstract
Airbus is investigating COTS multicore platforms for safety-critical avionics applications, pursuing helicopter-style autonomous and electric aircraft. These aircraft need to be ultra-lightweight for future mobility in the urban city landscape. As a step towards certification, Airbus identified the need for new methods that preserve the ARINC 653 single core schedule of a Helicopter Terrain Awareness and Warning System (HTAWS) application while scheduling additional safety-critical partitions on the other cores.
As some partitions in the HTAWS application are memory-intensive, static memory bandwidth throttling may lead to slow down of such partitions or provide only little remaining bandwidth to the other cores. Thus, there is a need for dynamic memory bandwidth isolation. This poses new challenges for scheduling, as execution times and scheduling become interdependent: scheduling requires execution times as input, which depends on memory latencies and contention from memory accesses of other cores - which are determined by scheduling. Furthermore, execution times depend on memory access patterns.
In this paper, we propose a method to solve this problem for slot-based time-triggered systems without requiring application source-code modifications using a number of dynamic memory bandwidth levels. It is NoC and DRAM controller contention-aware and based on the existing interference-sensitive WCET computation and the memory bandwidth throttling mechanism. It constructs schedule tables by assigning partitions and dynamic memory bandwidth to each slot on each core, considering worst case memory access patterns. Then at runtime, two servers - for processing time and memory bandwidth - run on each core, jointly controlling the contention between the cores and the amount of memory accesses per slot.
As a proof-of-concept, we use a constraint solver to construct tables. Experiments on the P4080 COTS multicore platform, using a research OS from Airbus and EEMBC benchmarks, demonstrate that our proposed method enables preserving existing schedules on a core while scheduling additional safety-critical partitions on other cores, and meets dynamic memory bandwidth isolation requirements.
Cite as
Ankit Agrawal, Gerhard Fohler, Johannes Freitag, Jan Nowotsch, Sascha Uhrig, and Michael Paulitsch. Contention-Aware Dynamic Memory Bandwidth Isolation with Predictability in COTS Multicores: An Avionics Case Study. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 2:1-2:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{agrawal_et_al:LIPIcs.ECRTS.2017.2,
author = {Agrawal, Ankit and Fohler, Gerhard and Freitag, Johannes and Nowotsch, Jan and Uhrig, Sascha and Paulitsch, Michael},
title = {{Contention-Aware Dynamic Memory Bandwidth Isolation with Predictability in COTS Multicores: An Avionics Case Study}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {2:1--2:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.2},
URN = {urn:nbn:de:0030-drops-71740},
doi = {10.4230/LIPIcs.ECRTS.2017.2},
annote = {Keywords: Dynamic memory bandwidth isolation, Safety-critical avionics, COTS multicores}
}
Document
WCET Derivation under Single Core Equivalence with Explicit Memory Budget Assignment
Abstract
In the last decade there has been a steady uptrend in the popularity of embedded multi-core platforms. This represents a turning point in the theory and implementation of real-time systems. From a real-time standpoint, however, the extensive sharing of hardware resources (e.g. caches, DRAM subsystem, I/O channels) represents a major source of unpredictability. Budget-based memory regulation (throttling) has been extensively studied to enforce a strict partitioning of the DRAM subsystem’s bandwidth. The common approach to analyze a task under memory bandwidth regulation is to consider the budget of the core where the task is executing, and assume the worst-case about the remaining cores' budgets.
In this work, we propose a novel analysis strategy to derive the WCET of a task under memory bandwidth regulation that takes into account the exact distribution of memory budgets to cores. In this sense, the proposed analysis represents a generalization of approaches that consider (i) even budget distribution across cores; and (ii) uneven but unknown (except for the core under analysis) budget assignment. By exploiting the additional piece of information, we show that it is possible to derive a more accurate WCET estimation. Our evaluations highlight that the proposed technique can reduce overestimation by 30% in average, and up to 60%, compared to the state of the art.
Cite as
Renato Mancuso, Rodolfo Pellizzoni, Neriman Tokcan, and Marco Caccamo. WCET Derivation under Single Core Equivalence with Explicit Memory Budget Assignment. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 3:1-3:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{mancuso_et_al:LIPIcs.ECRTS.2017.3,
author = {Mancuso, Renato and Pellizzoni, Rodolfo and Tokcan, Neriman and Caccamo, Marco},
title = {{WCET Derivation under Single Core Equivalence with Explicit Memory Budget Assignment}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {3:1--3:23},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.3},
URN = {urn:nbn:de:0030-drops-71684},
doi = {10.4230/LIPIcs.ECRTS.2017.3},
annote = {Keywords: real-time multicore, WCET, single-core equivalence, DRAM management, certification}
}
Document
LTZVisor: TrustZone is the Key
Abstract
Virtualization technology starts becoming more and more widespread in the embedded systems arena, driven by the upward trend for integrating multiple environments into the same hardware platform. The penalties incurred by standard software-based virtualization, altogether with the strict timing requirements imposed by real-time virtualization are pushing research towards hardware-assisted solutions. Among existing commercial off-the-shelf (COTS) technologies, ARM TrustZone promises to be a game-changer for virtualization, despite of this technology still being seen with a lot of obscurity and scepticism.
In this paper we present a Lightweight TrustZone-assisted Hypervisor (LTZVisor) as a tool to understand, evaluate and discuss the benefits and limitations of using TrustZone hardware to assist virtualization. We demonstrate how TrustZone can be adequately exploited for meeting the real-time needs, while presenting a low performance cost on running unmodified rich operating systems. While ARM continues to spread TrustZone technology from the applications processors to the smallest of microcontrollers, it is undeniable that this technology is gaining an increasing relevance. Our intent is to encourage research and drive the next generation of TrustZone-assisted virtualization solutions.
Cite as
Sandro Pinto, Jorge Pereira, Tiago Gomes, Adriano Tavares, and Jorge Cabral. LTZVisor: TrustZone is the Key. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 4:1-4:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{pinto_et_al:LIPIcs.ECRTS.2017.4,
author = {Pinto, Sandro and Pereira, Jorge and Gomes, Tiago and Tavares, Adriano and Cabral, Jorge},
title = {{LTZVisor: TrustZone is the Key}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {4:1--4:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.4},
URN = {urn:nbn:de:0030-drops-71535},
doi = {10.4230/LIPIcs.ECRTS.2017.4},
annote = {Keywords: hypervisor, virtualization, TrustZone, space and time partitioning, real-time, embedded systems}
}
Document
VCDC: The Virtualized Complicated Device Controller
Abstract
I/O virtualization enables time and space multiplexing of I/O devices, by mapping multiple logical I/O devices upon a smaller number of physical devices. However, due to the existence of additional virtualization layers, requesting an I/O from a guest virtual machine requires complicated sequences of operations. This leads to I/O performance losses, and makes precise timing of I/O operations unpredictable.
This paper proposes a hardware I/O virtualization system, termed the Virtualized Complicated Device Controller (VCDC). This I/O system allows user applications to access and operate I/O devices directly from guest VMs, and bypasses the guest OS, the Virtual Machine Monitor (VMM) and low layer I/O drivers. We show that the VCDC efficiently reduces the software overhead and enhances the I/O performance and timing predictability. Furthermore, VCDC also exhibits good scalability that can handle I/O requests from variable number of CPUs in a system.
Cite as
Zhe Jiang and Neil Audsley. VCDC: The Virtualized Complicated Device Controller. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 5:1-5:20, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{jiang_et_al:LIPIcs.ECRTS.2017.5,
author = {Jiang, Zhe and Audsley, Neil},
title = {{VCDC: The Virtualized Complicated Device Controller}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {5:1--5:20},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.5},
URN = {urn:nbn:de:0030-drops-71501},
doi = {10.4230/LIPIcs.ECRTS.2017.5},
annote = {Keywords: Many-core System, I/O Virtualization, Real-time I/O, Hardware Manager}
}
Document
VOSYSmonitor, a Low Latency Monitor Layer for Mixed-Criticality Systems on ARMv8-A
Abstract
With the emergence of multicore embedded System on Chip (SoC), the integration of several applications with different levels of criticality on the same platform is becoming increasingly popular. These platforms, known as mixed-criticality systems, need to meet numerous requirements such as real-time constraints, Operating System (OS) scheduling, memory and OSes isolation.
To construct mixed-criticality systems, various solutions, based on virtualization extensions, have been presented where OSes are contained in a Virtual Machine (VM) through the use of a hypervisor. However, such implementations usually lack hardware features to ensure a full isolation of other bus masters (e.g., Direct Memory Access (DMA) peripherals, Graphics Processing Unit (GPU)) between OSes. Furthermore on multicore implementation, one core is usually dedicated to one OS, causing CPU underutilization.
To address these issues, this paper presents VOSYSmonitor, a multi-core software layer, which allows the co-execution of a safety-critical Real-Time Operating System (RTOS) and a non-critical General Purpose Operating System (GPOS) on the same hardware ARMv8-A platform.
VOSYSmonitor main differentiation factors with the known solutions is the possibility for a processor to switch between secure and non-secure code execution at runtime. The partitioning is ensured by the ARM TrustZone technology, thus allowing to preserve the usage of virtualization features for the GPOS.
VOSYSmonitor architecture will be detailed in this paper, while benchmarking its performance versus other known solutions.
Cite as
Pierre Lucas, Kevin Chappuis, Michele Paolino, Nicolas Dagieu, and Daniel Raho. VOSYSmonitor, a Low Latency Monitor Layer for Mixed-Criticality Systems on ARMv8-A. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 6:1-6:18, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{lucas_et_al:LIPIcs.ECRTS.2017.6,
author = {Lucas, Pierre and Chappuis, Kevin and Paolino, Michele and Dagieu, Nicolas and Raho, Daniel},
title = {{VOSYSmonitor, a Low Latency Monitor Layer for Mixed-Criticality Systems on ARMv8-A}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {6:1--6:18},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.6},
URN = {urn:nbn:de:0030-drops-71543},
doi = {10.4230/LIPIcs.ECRTS.2017.6},
annote = {Keywords: VOSYSmonitor, ARM TrustZone, Mixed Criticality, Real Time}
}
Document
A Hierarchical Scheduling Model for Dynamic Soft-Realtime System
Abstract
We present a new hierarchical approximation and scheduling approach for applications and tasks with multiple modes on a single processor. Our model allows for a temporal and spatial distribution of the feasibility problem for a variable set of tasks with non-deterministic and fluctuating costs at runtime. In case of overloads an optimal degradation strategy selects one of several application modes or even temporarily deactivates applications. Hence, transient and permanent bottlenecks can be overcome with an optimal system quality, which is dynamically decided. This paper gives the first comprehensive and complete overview of all aspects of our research, including a novel CBS concept to confine entire applications, an evaluation of our system by using a video-on-demand application, an outline for adding further resource dimension, and aspects of our protoype implementation based on RTSJ.
Cite as
Vladimir Nikolov, Stefan Wesner, Eugen Frasch, and Franz J. Hauck. A Hierarchical Scheduling Model for Dynamic Soft-Realtime System. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 7:1-7:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{nikolov_et_al:LIPIcs.ECRTS.2017.7,
author = {Nikolov, Vladimir and Wesner, Stefan and Frasch, Eugen and Hauck, Franz J.},
title = {{A Hierarchical Scheduling Model for Dynamic Soft-Realtime System}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {7:1--7:23},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.7},
URN = {urn:nbn:de:0030-drops-71691},
doi = {10.4230/LIPIcs.ECRTS.2017.7},
annote = {Keywords: Real-Time, Scheduling, Hierarchical, Dynamic, ARTOS}
}
Document
Applying Real-Time Scheduling Theory to the Synchronous Data Flow Model of Computation
Abstract
Schedulability analysis techniques that are well understood within the real-time scheduling community are applied to the analysis of recurrent real-time workloads that are modeled using the synchronous data-flow graph (SDFG) model. An enhancement to the standard SDFG model is proposed, that permits the specification of a real-time latency constraint between a specified input and a specified output of an SDFG. A technique is derived for transforming such an enhanced SDFG to a collection of traditional 3-parameter sporadic tasks, thereby allowing for the analysis of systems of SDFG tasks using the methods and algorithms that have previously been developed within the real-time scheduling community for the analysis of systems of such sporadic tasks. The applicability of this approach is illustrated by applying prior results from real-time scheduling theory to construct an exact preemptive uniprocessor schedulability test for collections of recurrent processes that are each represented using the enhanced SDFG model.
Cite as
Abhishek Singh, Pontus Ekberg, and Sanjoy Baruah. Applying Real-Time Scheduling Theory to the Synchronous Data Flow Model of Computation. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 8:1-8:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{singh_et_al:LIPIcs.ECRTS.2017.8,
author = {Singh, Abhishek and Ekberg, Pontus and Baruah, Sanjoy},
title = {{Applying Real-Time Scheduling Theory to the Synchronous Data Flow Model of Computation}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {8:1--8:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.8},
URN = {urn:nbn:de:0030-drops-71517},
doi = {10.4230/LIPIcs.ECRTS.2017.8},
annote = {Keywords: Real-Time Systems, Synchronous Dataflow (SDF), Hard Real-Time Streaming Dataflow Applications, Algorithms}
}
Document
On the Pitfalls of Resource Augmentation Factors and Utilization Bounds in Real-Time Scheduling
Abstract
In this paper, we take a careful look at speedup factors, utilization bounds, and capacity augmentation bounds. These three metrics have been widely adopted in real-time scheduling research as the de facto standard theoretical tools for assessing scheduling algorithms and schedulability tests. Despite that, it is not always clear how researchers and designers should interpret or use these metrics. In studying this area, we found a number of surprising results, and related to them, ways in which the metrics may be misinterpreted or misunderstood. In this paper, we provide a perspective on the use of these metrics, guiding researchers on their meaning and interpretation, and helping to avoid pitfalls in their use. Finally, we propose and demonstrate the use of parametric augmentation functions as a means of providing nuanced information that may be more relevant in practical settings.
Cite as
Jian-Jia Chen, Georg von der Brüggen, Wen-Hung Huang, and Robert I. Davis. On the Pitfalls of Resource Augmentation Factors and Utilization Bounds in Real-Time Scheduling. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 9:1-9:25, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{chen_et_al:LIPIcs.ECRTS.2017.9,
author = {Chen, Jian-Jia and von der Br\"{u}ggen, Georg and Huang, Wen-Hung and Davis, Robert I.},
title = {{On the Pitfalls of Resource Augmentation Factors and Utilization Bounds in Real-Time Scheduling}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {9:1--9:25},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.9},
URN = {urn:nbn:de:0030-drops-71619},
doi = {10.4230/LIPIcs.ECRTS.2017.9},
annote = {Keywords: Real-time systems, speedup factors, utilization bounds, capacity augmentation bounds}
}
Document
Communication Centric Design in Complex Automotive Embedded Systems
Abstract
Automotive embedded applications like the engine management system are composed of multiple functional components that are tightly coupled via numerous communication dependencies and intensive data sharing, while also having real-time requirements. In order to cope with complexity, especially in multi-core settings, various communication mechanisms are used to ensure data consistency and temporal determinism along functional cause-effect chains. However, existing timing analysis methods generally only support very basic communication models that need to be extended to handle the analysis of industry grade problems which involve more complex communication semantics. In this work, we give an overview of communication semantics used in the automotive industry and the different constraints to be considered in the design process. We also propose a method for model transformation to increase the expressiveness of current timing analysis methods enabling them to work with more complex communication semantics. We demonstrate this transformation approach for concrete implementations of two communication semantics, namely, implicit and LET communication. We discuss the impact on end-to-end latencies and communication overheads based on a full blown engine management system.
Cite as
Arne Hamann, Dakshina Dasari, Simon Kramer, Michael Pressler, and Falk Wurst. Communication Centric Design in Complex Automotive Embedded Systems. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 10:1-10:20, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{hamann_et_al:LIPIcs.ECRTS.2017.10,
author = {Hamann, Arne and Dasari, Dakshina and Kramer, Simon and Pressler, Michael and Wurst, Falk},
title = {{Communication Centric Design in Complex Automotive Embedded Systems}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {10:1--10:20},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.10},
URN = {urn:nbn:de:0030-drops-71624},
doi = {10.4230/LIPIcs.ECRTS.2017.10},
annote = {Keywords: Communication semantics, logical execution time, implicit communication, automotive, embedded systems, scheduling simulation, Amalthea}
}
Document
Refinement of Workload Models for Engine Controllers by State Space Partitioning
Abstract
We study an engine control application where the behavior of engine controllers depends on the engine's rotational speed. For efficient and precise timing analysis, we use the Digraph Real-Time (DRT) task model to specify the workload of control tasks where we employ optimal control theory to faithfully calculate the respective minimum inter-release times. We show how DRT models can be refined by finer grained partitioning of the state space of the engine up to a model which enables an exact timing analysis. Compared to previously proposed methods which are either unsafe or pessimistic, our work provides both abstract and tight characterizations of the corresponding workload.
Cite as
Morteza Mohaqeqi, Jakaria Abdullah, Pontus Ekberg, and Wang Yi. Refinement of Workload Models for Engine Controllers by State Space Partitioning. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 11:1-11:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{mohaqeqi_et_al:LIPIcs.ECRTS.2017.11,
author = {Mohaqeqi, Morteza and Abdullah, Jakaria and Ekberg, Pontus and Yi, Wang},
title = {{Refinement of Workload Models for Engine Controllers by State Space Partitioning}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {11:1--11:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.11},
URN = {urn:nbn:de:0030-drops-71598},
doi = {10.4230/LIPIcs.ECRTS.2017.11},
annote = {Keywords: Engine Control Tasks, Schedulability Analysis, Minimum-Time Problem, DRT Task Model}
}
Document
The Multi-Domain Frame Packing Problem for CAN-FD
Abstract
The Controller Area Network with Flexible Data-Rate (CAN-FD) is a new communication protocol to meet the bandwidth requirements for the constantly growing volume of data exchanged in modern vehicles. The problem of frame packing for CAN-FD, as studied in the literature, assumes a single sub-system where one CAN-FD bus serves as the communication medium among several Electronic Control Units (ECUs). Modern automotive electronic systems, on the other hand, consist of several sub-systems, each facilitating a certain functional domain such as powertrain, chassis and suspension. A substantial fraction of all signals is exchanged across sub-systems. In this work, we study the frame packing problem for CAN-FD with multiple sub-systems, and propose a two-stage optimization framework. In the first stage, we pack the signals into frames with the objective of minimizing the bandwidth utilization. In the second stage, we extend Audsley's algorithm to assign priorities/identifiers to the frames. In case the resulting solution is not schedulable, our framework provides a potential repacking method. We propose two solution approaches: (a) an Integer Linear Programming (ILP) formulation that provides an optimal solution but is computationally expensive for industrial-size problems; and (b) a greedy heuristic that scales well and provides solutions that are comparable to optimal solutions. Experimental results show the efficiency of our optimization framework in achieving feasible solutions with low bandwidth utilization. The results also show a significant improvement over the case when there is no cross-domain consideration (as in prior work).
Cite as
Prachi Joshi, Haibo Zeng, Unmesh D. Bordoloi, Soheil Samii, S. S. Ravi, and Sandeep K. Shukla. The Multi-Domain Frame Packing Problem for CAN-FD. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 12:1-12:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{joshi_et_al:LIPIcs.ECRTS.2017.12,
author = {Joshi, Prachi and Zeng, Haibo and Bordoloi, Unmesh D. and Samii, Soheil and Ravi, S. S. and Shukla, Sandeep K.},
title = {{The Multi-Domain Frame Packing Problem for CAN-FD}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {12:1--12:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.12},
URN = {urn:nbn:de:0030-drops-71551},
doi = {10.4230/LIPIcs.ECRTS.2017.12},
annote = {Keywords: Frame Packing, CAN-FD, Integer Linear Programming, Audsley's Algorithm}
}
Document
Semi-Partitioned Scheduling of Dynamic Real-Time Workload: A Practical Approach Based on Analysis-Driven Load Balancing
Abstract
Recent work showed that semi-partitioned scheduling can achieve near-optimal schedulability performance, is simpler to implement compared to global scheduling, and less heavier in terms of runtime overhead, thus resulting in an excellent choice for implementing real-world systems. However, semi-partitioned scheduling typically leverages an off-line design to allocate tasks across the available processors, which requires a-priori knowledge of the workload. Conversely, several simple global schedulers, as global earliest-deadline first (G-EDF), can transparently support dynamic workload without requiring a task-allocation phase. Nonetheless, such schedulers exhibit poor worst-case performance.
This work proposes a semi-partitioned approach to efficiently schedule dynamic real-time workload on a multiprocessor system. A linear-time approximation for the C=D splitting scheme under partitioned EDF scheduling is first presented to reduce the complexity of online scheduling decisions. Then, a load-balancing algorithm is proposed for admitting new real-time workload in the system with limited workload re-allocation. A large-scale experimental study shows that the linear-time approximation has a very limited utilization loss compared to the exact technique and the proposed approach achieves very high schedulability performance, with a consistent improvement on G-EDF and pure partitioned EDF scheduling.
Cite as
Daniel Casini, Alessandro Biondi, and Giorgio Buttazzo. Semi-Partitioned Scheduling of Dynamic Real-Time Workload: A Practical Approach Based on Analysis-Driven Load Balancing. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 13:1-13:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{casini_et_al:LIPIcs.ECRTS.2017.13,
author = {Casini, Daniel and Biondi, Alessandro and Buttazzo, Giorgio},
title = {{Semi-Partitioned Scheduling of Dynamic Real-Time Workload: A Practical Approach Based on Analysis-Driven Load Balancing}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {13:1--13:23},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.13},
URN = {urn:nbn:de:0030-drops-71659},
doi = {10.4230/LIPIcs.ECRTS.2017.13},
annote = {Keywords: Semi-partitioned scheduling, dynamic workload, real-time}
}
Document
Cache-Conscious Offline Real-Time Task Scheduling for Multi-Core Processors
Abstract
Most schedulability analysis techniques for multi-core architectures assume a single Worst-Case Execution Time (WCET) per task, which is valid in all execution conditions. This assumption is too pessimistic for parallel applications running on multi-core architectures with local instruction or data caches, for which the WCET of a task depends on the cache contents at the beginning of its execution, itself depending on the task that was executed before the task under study.
In this paper, we propose two scheduling techniques for multi-core architectures equipped with local instruction and data caches. The two techniques schedule a parallel application modeled as a task graph, and generate a static partitioned non-preemptive schedule. We propose an optimal method, using an Integer Linear Programming (ILP) formulation, as well as a heuristic method based on list scheduling. Experimental results show that by taking into account the effect of private caches on tasks' WCETs, the length of generated schedules is significantly reduced as compared to schedules generated by cache-unaware scheduling methods. The observed schedule length reduction on streaming applications is 11% on average for the optimal method and 9% on average for the heuristic method.
Cite as
Viet Anh Nguyen, Damien Hardy, and Isabelle Puaut. Cache-Conscious Offline Real-Time Task Scheduling for Multi-Core Processors. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 14:1-14:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{nguyen_et_al:LIPIcs.ECRTS.2017.14,
author = {Nguyen, Viet Anh and Hardy, Damien and Puaut, Isabelle},
title = {{Cache-Conscious Offline Real-Time Task Scheduling for Multi-Core Processors}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {14:1--14:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.14},
URN = {urn:nbn:de:0030-drops-71642},
doi = {10.4230/LIPIcs.ECRTS.2017.14},
annote = {Keywords: Real-time scheduling, Cache-conscious scheduling, Many-core architectures, ILP, Static list scheduling}
}
Document
Optimal Dataflow Scheduling on a Heterogeneous Multiprocessor With Reduced Response Time Bounds
Abstract
Heterogeneous computing platforms with multiple types of computing resources have been widely used in many industrial systems to process dataflow tasks with pre-defined affinity of tasks to subgroups of resources. For many dataflow workloads with soft real-time requirements, guaranteeing fast and bounded response times is often the objective. This paper presents a new set of analysis techniques showing that a classical real-time scheduler, namely earliest-deadline first (EDF), is able to support dataflow tasks scheduled on such heterogeneous platforms with provably bounded response times while incurring no resource capacity loss, thus proving EDF to be an optimal solution for this scheduling problem. Experiments using synthetic workloads with widely varied parameters also demonstrate that the magnitude of the response time bounds yielded under the proposed analysis is reasonably small under all scenarios. Compared to the state-of-the-art soft real-time analysis techniques, our test yields a 68% reduction on response time bounds on average. This work demonstrates the potential of applying EDF into practical industrial systems containing dataflow-based workloads that desire guaranteed bounded response times.
Cite as
Zheng Dong, Cong Liu, Alan Gatherer, Lee McFearin, Peter Yan, and James H. Anderson. Optimal Dataflow Scheduling on a Heterogeneous Multiprocessor With Reduced Response Time Bounds. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 15:1-15:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{dong_et_al:LIPIcs.ECRTS.2017.15,
author = {Dong, Zheng and Liu, Cong and Gatherer, Alan and McFearin, Lee and Yan, Peter and Anderson, James H.},
title = {{Optimal Dataflow Scheduling on a Heterogeneous Multiprocessor With Reduced Response Time Bounds}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {15:1--15:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.15},
URN = {urn:nbn:de:0030-drops-71565},
doi = {10.4230/LIPIcs.ECRTS.2017.15},
annote = {Keywords: Real-time Scheduling, schedulability, heterogeneous multiprocessor}
}
Document
Design and Implementation of a Time Predictable Processor: Evaluation With a Space Case Study
Abstract
Embedded real-time systems like those found in automotive, rail and aerospace, steadily require higher levels of guaranteed computing performance (and hence time predictability) motivated by the increasing number of functionalities provided by software. However, high-performance processor design is driven by the average-performance needs of mainstream market. To make things worse, changing those designs is hard since the embedded real-time market is comparatively a small market. A path to address this mismatch is designing low-complexity hardware features that favor time predictability and can be enabled/disabled not to affect average performance when performance guarantees are not required. In this line, we present the lessons learned designing and implementing LEOPARD, a four-core processor facilitating measurement-based timing analysis (widely used in most domains). LEOPARD has been designed adding low-overhead hardware mechanisms to a LEON3 processor baseline that allow capturing the impact of jittery resources (i.e. with variable latency) in the measurements performed at analysis time. In particular, at core level we handle the jitter of caches, TLBs and variable-latency floating point units; and at the chip level, we deal with contention so that time-composable timing guarantees can be obtained. The result of our applied study with a Space application shows how per-resource jitter is controlled facilitating the computation of high-quality WCET estimates.
Cite as
Carles Hernández, Jaume Abella, Francisco J. Cazorla, Alen Bardizbanyan, Jan Andersson, Fabrice Cros, and Franck Wartel. Design and Implementation of a Time Predictable Processor: Evaluation With a Space Case Study. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 16:1-16:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{hernandez_et_al:LIPIcs.ECRTS.2017.16,
author = {Hern\'{a}ndez, Carles and Abella, Jaume and Cazorla, Francisco J. and Bardizbanyan, Alen and Andersson, Jan and Cros, Fabrice and Wartel, Franck},
title = {{Design and Implementation of a Time Predictable Processor: Evaluation With a Space Case Study}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {16:1--16:23},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.16},
URN = {urn:nbn:de:0030-drops-71737},
doi = {10.4230/LIPIcs.ECRTS.2017.16},
annote = {Keywords: Processor design, performance guarantees, multicore, Industrial case studies, Application of real-time technology in realistic systems}
}
Document
Budgeting Under-Specified Tasks for Weakly-Hard Real-Time Systems
Abstract
In this paper, we present an extension of slack analysis for budgeting in the design of weakly-hard real-time systems. During design, it often happens that some parts of a task set are fully specified while other parameters, e.g. regarding recovery or monitoring tasks, will be available only much later. In such cases, slack analysis can help anticipate how these missing parameters can influence the behavior of the whole system so that a resource budget can be allocated to them. It is, however, sufficient in many application contexts to budget these tasks in order to preserve weakly-hard rather than hard guarantees. We thus present an extension of slack analysis for deriving task budgets for systems with hard and weakly-hard requirements. This work is motivated by and validated on a realistic case study inspired by industrial practice.
Cite as
Zain A. H. Hammadeh, Sophie Quinton, Marco Panunzio, Rafik Henia, Laurent Rioux, and Rolf Ernst. Budgeting Under-Specified Tasks for Weakly-Hard Real-Time Systems. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 17:1-17:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{hammadeh_et_al:LIPIcs.ECRTS.2017.17,
author = {Hammadeh, Zain A. H. and Quinton, Sophie and Panunzio, Marco and Henia, Rafik and Rioux, Laurent and Ernst, Rolf},
title = {{Budgeting Under-Specified Tasks for Weakly-Hard Real-Time Systems}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {17:1--17:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.17},
URN = {urn:nbn:de:0030-drops-71636},
doi = {10.4230/LIPIcs.ECRTS.2017.17},
annote = {Keywords: Real-time, Weakly-hard, Slack analysis, Execution budget, Fixed priority}
}
Document
Mixed-Criticality Scheduling with Dynamic Redistribution of Shared Cache
Abstract
The design of mixed-criticality systems often involves painful tradeoffs between safety guarantees and performance. However, the use of more detailed architectural models in the design and analysis of scheduling arrangements for mixed-criticality systems can provide greater confidence in the analysis, but also opportunities for better performance. Motivated by this view, we propose an extension of Vestal's model for mixed-criticality multicore systems that (i) accounts for the per-task partitioning of the last-level cache and (ii) supports the dynamic reassignment, for better schedulability, of cache portions initially reserved for lower-criticality tasks to the higher-criticality tasks, when the system switches to high-criticality mode. To this model, we apply partitioned EDF scheduling with Ekberg and Yi's deadline-scaling technique. Our schedulability analysis and scalefactor calculation is cognisant of the cache resources assigned to each task, by using WCET estimates that take into account these resources. It is hence able to leverage the dynamic reconfiguration of the cache partitioning, at mode change, for better performance, in terms of provable schedulability. We also propose heuristics for partitioning the cache in low- and high-criticality mode, that promote schedulability. Our experiments with synthetic task sets, indicate tangible improvements in schedulability compared to a baseline cache-aware arrangement where there is no redistribution of cache resources from low- to high-criticality tasks in the event of a mode change.
Cite as
Muhammad Ali Awan, Konstantinos Bletsas, Pedro F. Souto, Benny Akesson, and Eduardo Tovar. Mixed-Criticality Scheduling with Dynamic Redistribution of Shared Cache. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 18:1-18:21, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{awan_et_al:LIPIcs.ECRTS.2017.18,
author = {Awan, Muhammad Ali and Bletsas, Konstantinos and Souto, Pedro F. and Akesson, Benny and Tovar, Eduardo},
title = {{Mixed-Criticality Scheduling with Dynamic Redistribution of Shared Cache}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {18:1--18:21},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.18},
URN = {urn:nbn:de:0030-drops-71710},
doi = {10.4230/LIPIcs.ECRTS.2017.18},
annote = {Keywords: Mixed Criticality Scheduling, Vestal Model, Dynamic Redistribution of Shared Cache, Shared Last-level Cache Analysis, Cache-aware Scheduling}
}
Document
Improving the Quality-of-Service for Scheduling Mixed-Criticality Systems on Multiprocessors
Abstract
The traditional Vestal's model of Mixed-Criticality (MC) systems was recently extended to Imprecise Mixed-Critical task model (IMC) to guarantee some minimum level of (degraded) service to the low-critical tasks even after the system switches to the high-critical behavior. This paper extends the IMC task model by associating specific Quality-of-Service (QoS) values with the low-critical tasks and proposes a fluid-based scheduling algorithm, called MCFQ, for such task model. The MCFQ algorithm allows some low-critical tasks to provide full service even during the high-critical behavior so that the QoS of the overall system is increased. To the best of our knowledge MCFQ is the first algorithm for IMC task sets considering multiprocessor platform and QoS values.
By extending the recently proposed MC-Fluid and MCF fluid-based multiprocessor scheduling algorithms for IMC task model, empirical results show that MCFQ algorithm can significantly improve the QoS of the system in comparison to that of both MC-Fluid and MCF. In addition, the schedulability performance of MCFQ is very close to the optimal MC-Fluid algorithm. Finally, we prove that the MCFQ algorithm has a speedup bound of 4/3, which is optimal for IMC tasks.
Cite as
Risat Mahmud Pathan. Improving the Quality-of-Service for Scheduling Mixed-Criticality Systems on Multiprocessors. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 19:1-19:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{pathan:LIPIcs.ECRTS.2017.19,
author = {Pathan, Risat Mahmud},
title = {{Improving the Quality-of-Service for Scheduling Mixed-Criticality Systems on Multiprocessors}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {19:1--19:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.19},
URN = {urn:nbn:de:0030-drops-71579},
doi = {10.4230/LIPIcs.ECRTS.2017.19},
annote = {Keywords: Mixed-Criticality Systems, Real-Time Systems, Multiprocessor Scheduling, Quality of Service, Imprecise Computation}
}
Document
Replica-Aware Co-Scheduling for Mixed-Criticality
Abstract
Cross-layer fault-tolerance solutions are the key to effectively and efficiently increase the reliability in future safety-critical real-time systems. Replicated software execution with hardware support for error detection is a cross-layer approach that exploits future many-core platforms to increase reliability without resorting to redundancy in hardware. The performance of such systems, however, strongly depends on the scheduler. Standard schedulers, such as Partitioned~Strict Priority Preemptive (SPP) and Time-Division Multiplexing (TDM)-based ones, although widely employed, provide poor performance in face of replicated execution. In this paper, we propose the replica-aware co-scheduling for mixed-critical systems. Experimental results show schedulability improvements of more than 1.5x when compared to TDM and 6.9x when compared to SPP.
Cite as
Eberle A. Rambo and Rolf Ernst. Replica-Aware Co-Scheduling for Mixed-Criticality. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 20:1-20:20, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{rambo_et_al:LIPIcs.ECRTS.2017.20,
author = {Rambo, Eberle A. and Ernst, Rolf},
title = {{Replica-Aware Co-Scheduling for Mixed-Criticality}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {20:1--20:20},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.20},
URN = {urn:nbn:de:0030-drops-71529},
doi = {10.4230/LIPIcs.ECRTS.2017.20},
annote = {Keywords: replicated execution, scheduling, fault-tolerance, real-time systems}
}
Document
Thermal Implications of Energy-Saving Schedulers
Abstract
In many real-time systems, continuous operation can raise processor temperature, potentially leading to system failure, bodily harm to users, or a reduction in the functional lifetime of a system. Static power dominates the total power consumption, and is also directly proportional to the operating temperature. This reduces the effectiveness of frequency scaling and necessitates the use of sleep states. In this work, we explore the relationship between energy savings and system temperature in the context of fixed-priority energy-saving schedulers, which utilize a processor’s deep-sleep state to save energy. We derive insights from a well-known thermal model, and are able to identify proactive design choices which are independent of system constants and can be used to reduce processor temperature. Our observations indicate that, while energy savings are key to lower temperatures, not all energy-efficient solutions yield low temperatures. Based on these insights, we propose the SysSleep and ThermoSleep algorithms, which enable a thermally-effective sleep schedule. We also derive a lower bound on the optimal temperature achievable by energy-saving schedulers. Additionally, we discuss partitioning and task phasing techniques for multi-core processors, which require all cores to synchronously transition into deep sleep, as well as those which support independent deep-sleep transitions. We observe that, while energy optimization is straightforward in some cases, the dependence of temperature on partitioning and task phasing makes temperature minimization non-trivial. Evaluations show that compared to the existing purely energy-efficient design methodology, our proposed techniques yield lower temperatures along with significant energy savings.
Cite as
Sandeep M. D'souza and Ragunathan (Raj) Rajkumar. Thermal Implications of Energy-Saving Schedulers. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 21:1-21:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{dsouza_et_al:LIPIcs.ECRTS.2017.21,
author = {D'souza, Sandeep M. and Rajkumar, Ragunathan (Raj)},
title = {{Thermal Implications of Energy-Saving Schedulers}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {21:1--21:23},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.21},
URN = {urn:nbn:de:0030-drops-71661},
doi = {10.4230/LIPIcs.ECRTS.2017.21},
annote = {Keywords: Thermal Analysis, Real-Time Scheduling}
}
Document
Energy-Efficient Multi-Core Scheduling for Real-Time DAG Tasks
Abstract
In this work, we study energy-aware real-time scheduling of a set of sporadic Directed Acyclic Graph (DAG) tasks with implicit deadlines. While meeting all real-time constraints, we try to identify the best task allocation and execution pattern such that the average power consumption of the whole platform is minimized. To the best of our knowledge, this is the first work that addresses the power consumption issue in scheduling multiple DAG tasks on multi-cores and allows intra-task processor sharing. We first adapt the decomposition-based framework for federated scheduling and propose an energy-sub-optimal scheduler. Then we derive an approximation algorithm to identify processors to be merged together for further improvements in energy-efficiency and to prove the bound of the approximation ratio. We perform a simulation study to demonstrate the effectiveness and efficiency of the proposed scheduling. The simulation results show that our algorithms achieve an energy saving of 27% to 41% compared to existing DAG task
schedulers.
Cite as
Zhishan Guo, Ashikahmed Bhuiyan, Abusayeed Saifullah, Nan Guan, and Haoyi Xiong. Energy-Efficient Multi-Core Scheduling for Real-Time DAG Tasks. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 22:1-22:21, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{guo_et_al:LIPIcs.ECRTS.2017.22,
author = {Guo, Zhishan and Bhuiyan, Ashikahmed and Saifullah, Abusayeed and Guan, Nan and Xiong, Haoyi},
title = {{Energy-Efficient Multi-Core Scheduling for Real-Time DAG Tasks}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {22:1--22:21},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.22},
URN = {urn:nbn:de:0030-drops-71675},
doi = {10.4230/LIPIcs.ECRTS.2017.22},
annote = {Keywords: Parallel task, Real-time scheduling, Energy minimization, Convex optimization}
}
Document
Contego: An Adaptive Framework for Integrating Security Tasks in Real-Time Systems
Abstract
Embedded real-time systems (RTS) are pervasive. Many modern RTS are exposed to unknown security flaws, and threats to RTS are growing in both number and sophistication. However, until recently, cyber-security considerations were an afterthought in the design of such systems. Any security mechanisms integrated into RTS must (a) co-exist with the real-time tasks in the system and (b) operate without impacting the timing and safety constraints of the control logic. We introduce Contego, an approach to integrating security tasks into RTS without affecting temporal requirements. Contego is specifically designed for legacy systems, viz., the real-time control systems in which major alterations of the system parameters for constituent tasks is not always feasible. Contego combines the concept of opportunistic execution with hierarchical scheduling to maintain compatibility with legacy systems while still providing flexibility by allowing security tasks to operate in different modes. We also define a metric to measure the effectiveness of such integration. We evaluate Contego using synthetic workloads as well as with an implementation on a realistic embedded platform (an open-source ARM CPU running real-time Linux).
Cite as
Monowar Hasan, Sibin Mohan, Rodolfo Pellizzoni, and Rakesh B. Bobba. Contego: An Adaptive Framework for Integrating Security Tasks in Real-Time Systems. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 23:1-23:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{hasan_et_al:LIPIcs.ECRTS.2017.23,
author = {Hasan, Monowar and Mohan, Sibin and Pellizzoni, Rodolfo and Bobba, Rakesh B.},
title = {{Contego: An Adaptive Framework for Integrating Security Tasks in Real-Time Systems}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {23:1--23:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.23},
URN = {urn:nbn:de:0030-drops-71728},
doi = {10.4230/LIPIcs.ECRTS.2017.23},
annote = {Keywords: Real-Time Systems, Security, Hierarchical Scheduling}
}
Document
WCET-Driven Dynamic Data Scratchpad Management With Compiler-Directed Prefetching
Abstract
In recent years, the real-time community has produced a variety of approaches targeted at managing on-chip memory (scratchpads and caches) in a predictable way. However, to obtain safe WCET bounds, such techniques generally assume that the processor is stalled while waiting to reload the content of the on-chip memory; hence, they are less effective at hiding main memory latency compared to speculation-based techniques, such as hardware prefetching, that are largely used in general-purpose systems. In this work, we introduce a novel compiler-directed prefetching scheme for scratchpad memory that effectively hides the latency of main memory accesses by overlapping data transfers with the program execution. We implement and test an automated program compilation and optimization flow within the LLVM framework, and we show how to obtain improved WCET bounds through static analysis.
Cite as
Muhammad Refaat Soliman and Rodolfo Pellizzoni. WCET-Driven Dynamic Data Scratchpad Management With Compiler-Directed Prefetching. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 24:1-24:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{soliman_et_al:LIPIcs.ECRTS.2017.24,
author = {Soliman, Muhammad Refaat and Pellizzoni, Rodolfo},
title = {{WCET-Driven Dynamic Data Scratchpad Management With Compiler-Directed Prefetching}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {24:1--24:23},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.24},
URN = {urn:nbn:de:0030-drops-71756},
doi = {10.4230/LIPIcs.ECRTS.2017.24},
annote = {Keywords: scratchpad, LLVM, prefetching, real-time, genetic algorithm}
}
Document
A Linux Real-Time Packet Scheduler for Reliable Static SDN Routing
Abstract
In a distributed computing environment, guaranteeing the hard deadline for real-time messages is essential to ensure schedulability of real-time tasks. Since capabilities of the shared resources for transmission are limited, e.g., the buffer size is limited on network devices, it becomes a challenge to design an effective and feasible resource sharing policy based on both the demand of real-time packet transmissions and the limitation of resource capabilities. We address this challenge in two cooperative mechanisms. First, we design a static routing algorithm to find forwarding paths for packets to guarantee their hard deadlines. The routing algorithm employs a validation-based backtracking procedure capable of deriving the demand of a set of real-time packets on each shared network device, and it checks whether this demand can be met on the device. Second, we design a packet scheduler that runs on network devices to transmit messages according to our routing requirements. We implement these mechanisms on virtual software-defined network (SDN) switches and evaluate them on real hardware in a local cluster to demonstrate the feasibility and effectiveness of our routing algorithm and packet scheduler.
Cite as
Tao Qian, Frank Mueller, and Yufeng Xin. A Linux Real-Time Packet Scheduler for Reliable Static SDN Routing. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 25:1-25:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{qian_et_al:LIPIcs.ECRTS.2017.25,
author = {Qian, Tao and Mueller, Frank and Xin, Yufeng},
title = {{A Linux Real-Time Packet Scheduler for Reliable Static SDN Routing}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {25:1--25:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.25},
URN = {urn:nbn:de:0030-drops-71707},
doi = {10.4230/LIPIcs.ECRTS.2017.25},
annote = {Keywords: Real-time Networks, Packet Scheduling, Deadline Guarantee}
}
Document
Write-Back Caches in WCET Analysis
Abstract
Write-back caches are a popular choice in embedded microprocessors as they promise higher performance than write-through caches. So far, however, their use in hard real-time systems has been prohibited by the lack of adequate worst-case execution time (WCET) analysis support.
In this paper, we introduce a new approach to statically analyze the behavior of write-back caches. Prior work took an "eviction-focussed perspective", answering for each potential cache miss: May this miss evict a dirty cache line and thus cause a write back? We complement this approach by exploring a "store-focussed perspective", answering for each store: May this store dirtify a clean cache line and thus cause a write back later on?
Experimental evaluation demonstrates substantial precision improvements when both perspectives are combined. For most benchmarks, write-back caches are then preferable to write-through caches in terms of the computed WCET bounds.
Cite as
Tobias Blaß, Sebastian Hahn, and Jan Reineke. Write-Back Caches in WCET Analysis. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 26:1-26:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@InProceedings{bla_et_al:LIPIcs.ECRTS.2017.26,
author = {Bla{\ss}, Tobias and Hahn, Sebastian and Reineke, Jan},
title = {{Write-Back Caches in WCET Analysis}},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
pages = {26:1--26:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-037-8},
ISSN = {1868-8969},
year = {2017},
volume = {76},
editor = {Bertogna, Marko},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.26},
URN = {urn:nbn:de:0030-drops-71589},
doi = {10.4230/LIPIcs.ECRTS.2017.26},
annote = {Keywords: write-back caches, real-time systems, WCET analysis, cache analysis}
}