Creative Commons Attribution 3.0 Germany license (CC BY 3.0 DE)when quoting this document, please refer to the following
DOI: 10.4230/DARTS.4.2.5
URN: urn:nbn:de:0030-drops-89732
URL: https://drops.dagstuhl.de/opus/volltexte/2018/8973/
Awan, Muhammad Ali ; Souto, Pedro F. ; Bletsas, Konstantinos ; Akesson, Benny ; Tovar, Eduardo
Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact)
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Abstract
This artifact demonstrates the performance of the proposed worst-case memory stall analysis for a memory-regulated multicore with two memory controllers. The memory stall analysis is implemented in Java along with five different stall-cognisant bandwidth-to-core and task-to-core assignment heuristics. It evaluates the performance of these heuristics in terms of schedulability via experiments with synthetic task sets capturing different system characteristics. It also quantifies the cost in terms of extra stall for letting all cores benefit from the memory space offered by both controllers on the given multicore platform.
BibTeX - Entry
@Article{awan_et_al:DARTS:2018:8973,
author = {Muhammad Ali Awan and Pedro F. Souto and Konstantinos Bletsas and Benny Akesson and Eduardo Tovar},
title = {{Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact)}},
pages = {5:1--5:3},
journal = {Dagstuhl Artifacts Series},
ISSN = {2509-8195},
year = {2018},
volume = {4},
number = {2},
publisher = {Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik},
address = {Dagstuhl, Germany},
URL = {http://drops.dagstuhl.de/opus/volltexte/2018/8973},
URN = {urn:nbn:de:0030-drops-89732},
doi = {10.4230/DARTS.4.2.5},
annote = {Keywords: multiple memory controllers, memory regulation, multicore}
}
| Keywords: | multiple memory controllers, memory regulation, multicore | |
| Seminar: | DARTS, Volume 4, Issue 2 | |
| Related Scholarly Article: | http://dx.doi.org/10.4230/LIPIcs.ECRTS.2018.2 | |
| Issue date: | 2018 | |
| Date of publication: | 20.06.2018 |
