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Just-In-Time Composition of Reconfigurable Overlays (Invited Talk)

Authors Rafael Zamacola , Andrés Otero , Alfonso Rodríguez , Eduardo de la Torre

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Author Details

Rafael Zamacola
  • Centro de Electrónica Industrial, Universidad Politécnica de Madrid, Spain
Andrés Otero
  • Centro de Electrónica Industrial, Universidad Politécnica de Madrid, Spain
Alfonso Rodríguez
  • Centro de Electrónica Industrial, Universidad Politécnica de Madrid, Spain
Eduardo de la Torre
  • Centro de Electrónica Industrial, Universidad Politécnica de Madrid, Spain

Funding

This project has been funded by the Spanish Ministry for Science and Innovation under the project TALENT (ref. PID2020-116417RB-C42).

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Rafael Zamacola, Andrés Otero, Alfonso Rodríguez, and Eduardo de la Torre. Just-In-Time Composition of Reconfigurable Overlays (Invited Talk). In 13th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 11th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2022). Open Access Series in Informatics (OASIcs), Volume 100, pp. 2:1-2:13, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2022) https://doi.org/10.4230/OASIcs.PARMA-DITAM.2022.2

Abstract

This paper describes a framework supporting the automatic composition of reconfigurable overlays laid on top of an FPGA to offload computing-intensive sections of a given application, from an embedded processor to a loosely coupled reconfigurable accelerator. Overlays provide an abstraction layer acting as an intermediate fabric between users' applications and the FPGA fabric. Among the existing flavors, the overlay template proposed in this work is based on a coarse-grain reconfigurable architecture featuring word-level operators, reducing long place-and-route times associated with FPGA designs. The proposed overlays are composed at run-time using a tile-based approach, in which pre-synthesized processing elements are stitched together following a 2D grid pattern and using dynamic and partial reconfiguration. The proposed reconfigurable architecture is accompanied by an automated toolchain that, relying on an LLVM intermediate representation, automatically converts the source code to a data-flow graph that is afterward mapped onto the overlay. A mapping example is provided in this paper to show the possibilities enabled by the framework, including loop mapping and loop unrolling support, features originally described in this work.

Subject Classification

ACM Subject Classification
  • Hardware → High-level and register-transfer level synthesis
Keywords
  • FPGA
  • Dynamic Partial Reconfiguration
  • Overlay
  • LLVM
  • Compilation

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