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Multithread Accelerators on FPGAs: A Dataflow-Based Approach

Authors Francesco Ratto , Stefano Esposito , Carlo Sau , Luigi Raffo , Francesca Palumbo

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Author Details

Francesco Ratto
  • Università degli Studi di Cagliari, Italy
Stefano Esposito
  • Università degli Studi di Cagliari, Italy
Carlo Sau
  • Università degli Studi di Cagliari, Italy
Luigi Raffo
  • Università degli Studi di Cagliari, Italy
Francesca Palumbo
  • Università degli Studi di Sassari, Italy

Funding

Prof. Palumbo is grateful to the University of Sassari that supported her studies on this topic through the "fondo di Ateneo per la ricerca 2020".

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Francesco Ratto, Stefano Esposito, Carlo Sau, Luigi Raffo, and Francesca Palumbo. Multithread Accelerators on FPGAs: A Dataflow-Based Approach. In 13th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 11th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2022). Open Access Series in Informatics (OASIcs), Volume 100, pp. 6:1-6:14, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2022) https://doi.org/10.4230/OASIcs.PARMA-DITAM.2022.6

Abstract

Multithreading is a well-known technique for general-purpose systems to deliver a substantial performance gain, raising resource efficiency by exploiting underutilization periods. With the increase of specialized hardware, resource efficiency became fundamental to master the introduced overhead of such kind of devices. In this work, we propose a model-based approach for designing specialized multithread hardware accelerators. This novel approach exploits dataflow models of applications and tagged tokens to let the resulting hardware support concurrent threads without the need to replicate the whole accelerator. Assessment is carried out over different versions of an accelerator for a compute-intensive step of modern video coding algorithms, under several feeding configurations. Results highlight that the proposed multithread accelerators achieve a valuable tradeoff: saving computational resources with respect to replicated parallel single-thread accelerators, while guaranteeing shorter waiting, response, and elaboration time than a unique single-thread accelerator multiplexed in time.

Subject Classification

ACM Subject Classification
  • Computer systems organization → Data flow architectures
  • Computing methodologies → Concurrent algorithms
  • Hardware → Best practices for EDA
Keywords
  • multithreading
  • dataflow
  • hardware acceleration
  • heterogeneous systems
  • tagged dataflow

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