Creative Commons Attribution 4.0 license (CC BY 4.0)when quoting this document, please refer to the following
DOI: 10.4230/OASIcs.WCET.2022.1
URN: urn:nbn:de:0030-drops-166231
URL: https://drops.dagstuhl.de/opus/volltexte/2022/16623/
Degioanni, Théo ; Puaut, Isabelle
StAMP: Static Analysis of Memory Access Profiles for Real-Time Tasks
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Abstract
Accesses to shared resources in multi-core systems raise predictability issues. The delay in accessing a resource for a task executing on a core depends on concurrent resource sharing from tasks executing on the other cores. In this paper, we present StAMP, a compiler technique that splits the code of tasks into a sequence of code intervals intervals, each with a distinct worst-case memory access profile. The intervals identified by StAMP can serve as inputs to scheduling techniques for a tight calculation of worst-case delays of memory accesses. The provided information can also ease the design of mechanisms that avoid and/or control interference between tasks at run-time. An important feature of StAMP compared to related work lies in its ability to link back time intervals to unique locations in the code of tasks, allowing easy implementation of elaborate run-time decisions related to interference management.
BibTeX - Entry
@InProceedings{degioanni_et_al:OASIcs.WCET.2022.1,
author = {Degioanni, Th\'{e}o and Puaut, Isabelle},
title = {{StAMP: Static Analysis of Memory Access Profiles for Real-Time Tasks}},
booktitle = {20th International Workshop on Worst-Case Execution Time Analysis (WCET 2022)},
pages = {1:1--1:13},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-244-0},
ISSN = {2190-6807},
year = {2022},
volume = {103},
editor = {Ballabriga, Cl\'{e}ment},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/opus/volltexte/2022/16623},
URN = {urn:nbn:de:0030-drops-166231},
doi = {10.4230/OASIcs.WCET.2022.1},
annote = {Keywords: Worst-Case Execution Time Estimation, Static Analysis, Multicore, Interference, Implicit Path Enumeration Technique}
}
| Keywords: | Worst-Case Execution Time Estimation, Static Analysis, Multicore, Interference, Implicit Path Enumeration Technique | |
| Seminar: | 20th International Workshop on Worst-Case Execution Time Analysis (WCET 2022) | |
| Issue date: | 2022 | |
| Date of publication: | 14.07.2022 | |
| Supplementary Material: | Text (Appendix): https://files.inria.fr/pacap/puaut/papers/WCET_2022_appendix.pdf |
