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Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments

Authors Michele Piccoli , Davide Zoni , William Fornaciari , Giuseppe Massari , Marco Cococcioni, Federico Rossi, Sergio Saponara, Emanuele Ruffaldi

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Author Details

Michele Piccoli
  • Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Polytechnic University of Milano, Italy
Davide Zoni
  • Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Polytechnic University of Milano, Italy
William Fornaciari
  • Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Polytechnic University of Milano, Italy
Giuseppe Massari
  • Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Polytechnic University of Milano, Italy
Marco Cococcioni
  • Dipartimento di Ingegneria dell'Informazione, University of Pisa, Italy
Federico Rossi
  • Dipartimento di Ingegneria dell'Informazione, University of Pisa, Italy
Sergio Saponara
  • Dipartimento di Ingegneria dell'Informazione, University of Pisa, Italy
Emanuele Ruffaldi
  • MMI spa, Pisa, Italy

Funding

Work partially supported by H2020 projects EPI-SGA2 (grant no. 101036168, https://www.european-processor-initiative.eu/) and TEXTAROSSA (grant no. 956831, https://textarossa.eu/).

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Michele Piccoli, Davide Zoni, William Fornaciari, Giuseppe Massari, Marco Cococcioni, Federico Rossi, Sergio Saponara, and Emanuele Ruffaldi. Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments. In 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023). Open Access Series in Informatics (OASIcs), Volume 107, pp. 6:1-6:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023) https://doi.org/10.4230/OASIcs.PARMA-DITAM.2023.6

Abstract

Since its introduction in 2017, the Posit™ format for representing real numbers has attracted a lot of interest, as an alternative to IEEE 754 floating point representation. Several hardware implementations of arithmetic operations between posit numbers have also been proposed in recent years. In this work, we analyze the dynamic power consumption of the Full Posit Processing Unit (FPPU) recently developed at the University of Pisa. Experimental results show that we can model the dynamic power consumption of the FPPU with an acceptable approximation error from 2.84% (32-bit FPPU) to 7.32% (8-bit FPPU). Furthermore, from the synthesis of the power monitoring unit alongside the FPPU we demonstrate that the additional power module has an area cost that goes from ∼5% (32-bit FPPU) to ∼30% (8-bit FPPU) of the total unit area occupation.

Subject Classification

ACM Subject Classification
  • Hardware → Power estimation and optimization
  • Hardware → Arithmetic and datapath circuits
  • Hardware → Reconfigurable logic and FPGAs
Keywords
  • power estimation
  • computer arithmetic
  • posit numbers

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