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DOI: 10.4230/LIPIcs.ECRTS.2024.16

Analysis of TSN Time-Aware Shapers Using Schedule Abstraction Graphs

Authors: Srinidhi Srinivasan, Geoffrey Nelissen, Reinder J. Bril, and Nirvana Meratnia

Published in: LIPIcs, Volume 298, 36th Euromicro Conference on Real-Time Systems (ECRTS 2024)

Abstract

IEEE Time-Sensitive Networking (TSN) is one of the main solutions considered by the industry to support time-sensitive communication in data-intensive safety-critical and mission-critical applications such as autonomous driving and smart manufacturing. IEEE TSN standardizes several mechanisms to support real-time traffic on Ethernet networks. Time-Aware Shapers (TAS) (IEEE 802.1Qbv) is the standardized mechanisms of TSN that is usually considered to provide the most deterministic behavior for packet forwarding. TAS regulates when traffic classes may forward incoming packets to the egress of a TSN switch using gates that are opened and closed according to a time-triggered schedule. State-of-the-art solutions to configure or analyze TAS do not allow for multiple traffic classes to have their TAS gates opened at the same time according to any arbitrary schedule. In this paper, we present the first response-time analysis for traffic shaped with TAS where no restriction is enforced on the gate schedule. The proposed analysis is exact. It is a non-trivial variant of the schedule abstraction graph analysis framework [Nasri and Brandenburg, 2017]. Experiments confirm the usefulness of the proposed analysis and show that it is promising for doing design-space exploration where non-conventional TAS gates configurations are investigated to, for instance, improve average-case performance without degrading the worst-case.

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Srinidhi Srinivasan, Geoffrey Nelissen, Reinder J. Bril, and Nirvana Meratnia. Analysis of TSN Time-Aware Shapers Using Schedule Abstraction Graphs. In 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 298, pp. 16:1-16:24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)

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@InProceedings{srinivasan_et_al:LIPIcs.ECRTS.2024.16,
  author =	{Srinivasan, Srinidhi and Nelissen, Geoffrey and Bril, Reinder J. and Meratnia, Nirvana},
  title =	{{Analysis of TSN Time-Aware Shapers Using Schedule Abstraction Graphs}},
  booktitle =	{36th Euromicro Conference on Real-Time Systems (ECRTS 2024)},
  pages =	{16:1--16:24},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-324-9},
  ISSN =	{1868-8969},
  year =	{2024},
  volume =	{298},
  editor =	{Pellizzoni, Rodolfo},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2024.16},
  URN =		{urn:nbn:de:0030-drops-203198},
  doi =		{10.4230/LIPIcs.ECRTS.2024.16},
  annote =	{Keywords: TSN, Time-Aware Shapers, TAS, SAG, Schedule Abstraction, latency}
}

Document

DOI: 10.4230/LITES-v004-i002-a003

Per Processor Spin-Based Protocols for Multiprocessor Real-Time Systems

Authors: Sara Afshar, Moris Behnam, Reinder J. Bril, and Thomas Nolte

Published in: LITES, Volume 4, Issue 2 (2017). Leibniz Transactions on Embedded Systems, Volume 4, Issue 2

Abstract

This paper investigates preemptive spin-based global resource sharing protocols for resource-constrained real-time embedded multi-core systems based on partitioned fixed-priority preemptive scheduling. We present preemptive spin-based protocols that feature (i) an increased schedulability ratio of task sets and reduced response jitter of tasks compared to the classical non-preemptive spin-based protocol, (ii) similar memory requirements for the administration of waiting tasks as for the non-preemptive protocol whilst only causing (iii) a minimal increase of the minimal number of required stacks per core from one to at most two, and (iv) strong progress guarantees to tasks. We complement these protocols with a unified worst-case response time analysis that specializes to the classical analysis for the non-preemptive protocol. The paper includes a comparative evaluation of the preemptive protocols and the non-preemptive protocol based on synthetic data.

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Sara Afshar, Moris Behnam, Reinder J. Bril, and Thomas Nolte. Per Processor Spin-Based Protocols for Multiprocessor Real-Time Systems. In LITES, Volume 4, Issue 2 (2017). Leibniz Transactions on Embedded Systems, Volume 4, Issue 2, pp. 03:1-03:30, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018)

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@Article{afshar_et_al:LITES-v004-i002-a003,
  author =	{Afshar, Sara and Behnam, Moris and Bril, Reinder J. and Nolte, Thomas},
  title =	{{Per Processor Spin-Based Protocols for Multiprocessor Real-Time Systems}},
  journal =	{Leibniz Transactions on Embedded Systems},
  pages =	{03:1--03:30},
  ISSN =	{2199-2002},
  year =	{2018},
  volume =	{4},
  number =	{2},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/LITES-v004-i002-a003},
  doi =		{10.4230/LITES-v004-i002-a003},
  annote =	{Keywords: Resource sharing, Real-time systems, Multiprocessors, Spin-locks}
}

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Documents authored by Bril, Reinder J.

Analysis of TSN Time-Aware Shapers Using Schedule Abstraction Graphs

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Per Processor Spin-Based Protocols for Multiprocessor Real-Time Systems

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