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Documents authored by Hahn, Sebastian

Document
DOI: 10.4230/OASIcs.WCET.2022.2
LLVMTA: An LLVM-Based WCET Analysis Tool

Authors: Sebastian Hahn, Michael Jacobs, Nils Hölscher, Kuan-Hsun Chen, Jian-Jia Chen, and Jan Reineke

Published in: OASIcs, Volume 103, 20th International Workshop on Worst-Case Execution Time Analysis (WCET 2022)

Abstract
We present llvmta, an academic WCET analysis tool based on the LLVM compiler infrastructure. It aims to enable the evaluation of novel WCET analysis approaches in a state-of-the-art analysis framework without dealing with the complexity of modeling real-world hardware architectures. We discuss the main design decisions and interfaces that allow to implement new analysis approaches. Finally, we highlight various existing research projects whose evaluation has been enabled by llvmta.
Cite as

Sebastian Hahn, Michael Jacobs, Nils Hölscher, Kuan-Hsun Chen, Jian-Jia Chen, and Jan Reineke. LLVMTA: An LLVM-Based WCET Analysis Tool. In 20th International Workshop on Worst-Case Execution Time Analysis (WCET 2022). Open Access Series in Informatics (OASIcs), Volume 103, pp. 2:1-2:17, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2022)

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@InProceedings{hahn_et_al:OASIcs.WCET.2022.2,
  author =	{Hahn, Sebastian and Jacobs, Michael and H\"{o}lscher, Nils and Chen, Kuan-Hsun and Chen, Jian-Jia and Reineke, Jan},
  title =	{{LLVMTA: An LLVM-Based WCET Analysis Tool}},
  booktitle =	{20th International Workshop on Worst-Case Execution Time Analysis (WCET 2022)},
  pages =	{2:1--2:17},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-244-0},
  ISSN =	{2190-6807},
  year =	{2022},
  volume =	{103},
  editor =	{Ballabriga, Cl\'{e}ment},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2022.2},
  URN =		{urn:nbn:de:0030-drops-166242},
  doi =		{10.4230/OASIcs.WCET.2022.2},
  annote =	{Keywords: WCET analysis, low-level analysis, LLVM}
}
Document
DOI: 10.4230/OASIcs.WCET.2018.7
Experimental Evaluation of Cache-Related Preemption Delay Aware Timing Analysis

Authors: Darshit Shah, Sebastian Hahn, and Jan Reineke

Published in: OASIcs, Volume 63, 18th International Workshop on Worst-Case Execution Time Analysis (WCET 2018)

Abstract
In the presence of caches, preemptive scheduling may incur a significant overhead referred to as cache-related preemption delay (CRPD). CRPD is caused by preempting tasks evicting cached memory blocks of preempted tasks, which have to be reloaded when the preempted tasks resume their execution. In this paper we experimentally evaluate state-of-the-art techniques to account for the CRPD during timing analysis. We find that purely synthetically-generated task sets may yield misleading conclusions regarding the relative precision of different CRPD analysis techniques and the impact of CRPD on schedulability in general. Based on task characterizations obtained by static worst-case execution time (WCET) analysis, we shed new light on the state of the art.
Cite as

Darshit Shah, Sebastian Hahn, and Jan Reineke. Experimental Evaluation of Cache-Related Preemption Delay Aware Timing Analysis. In 18th International Workshop on Worst-Case Execution Time Analysis (WCET 2018). Open Access Series in Informatics (OASIcs), Volume 63, pp. 7:1-7:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018)

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@InProceedings{shah_et_al:OASIcs.WCET.2018.7,
  author =	{Shah, Darshit and Hahn, Sebastian and Reineke, Jan},
  title =	{{Experimental Evaluation of Cache-Related Preemption Delay Aware Timing Analysis}},
  booktitle =	{18th International Workshop on Worst-Case Execution Time Analysis (WCET 2018)},
  pages =	{7:1--7:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-073-6},
  ISSN =	{2190-6807},
  year =	{2018},
  volume =	{63},
  editor =	{Brandner, Florian},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2018.7},
  URN =		{urn:nbn:de:0030-drops-97532},
  doi =		{10.4230/OASIcs.WCET.2018.7},
  annote =	{Keywords: real-time systems, timing analysis, cache-related preemption delay}
}
Document
DOI: 10.4230/LIPIcs.ECRTS.2017.26
Write-Back Caches in WCET Analysis

Authors: Tobias Blaß, Sebastian Hahn, and Jan Reineke

Published in: LIPIcs, Volume 76, 29th Euromicro Conference on Real-Time Systems (ECRTS 2017)

Abstract
Write-back caches are a popular choice in embedded microprocessors as they promise higher performance than write-through caches. So far, however, their use in hard real-time systems has been prohibited by the lack of adequate worst-case execution time (WCET) analysis support. In this paper, we introduce a new approach to statically analyze the behavior of write-back caches. Prior work took an "eviction-focussed perspective", answering for each potential cache miss: May this miss evict a dirty cache line and thus cause a write back? We complement this approach by exploring a "store-focussed perspective", answering for each store: May this store dirtify a clean cache line and thus cause a write back later on? Experimental evaluation demonstrates substantial precision improvements when both perspectives are combined. For most benchmarks, write-back caches are then preferable to write-through caches in terms of the computed WCET bounds.
Cite as

Tobias Blaß, Sebastian Hahn, and Jan Reineke. Write-Back Caches in WCET Analysis. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 26:1-26:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)

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@InProceedings{bla_et_al:LIPIcs.ECRTS.2017.26,
  author =	{Bla{\ss}, Tobias and Hahn, Sebastian and Reineke, Jan},
  title =	{{Write-Back Caches in WCET Analysis}},
  booktitle =	{29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
  pages =	{26:1--26:22},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-037-8},
  ISSN =	{1868-8969},
  year =	{2017},
  volume =	{76},
  editor =	{Bertogna, Marko},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.26},
  URN =		{urn:nbn:de:0030-drops-71589},
  doi =		{10.4230/LIPIcs.ECRTS.2017.26},
  annote =	{Keywords: write-back caches, real-time systems, WCET analysis, cache analysis}
}
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