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Documents authored by Herkersdorf, Andreas

Document
DOI: 10.4230/DagRep.3.1.149
Multicore Enablement for Embedded and Cyber Physical Systems (Dagstuhl Seminar 13052)

Authors: Andreas Herkersdorf and Michael Paulitsch

Published in: Dagstuhl Reports, Volume 3, Issue 1 (2013)

Abstract
This report documents the program and the outcomes of Dagstuhl Seminar 13052 "Multicore Enablement for Embedded and Cyber Physical Systems. During the seminar the participants from industry and academia actively discussed chances and problems of multicore processors in embedded in cyber-physical systems. The focus of the seminar was on the exchange of experiences and discussion of the challenges of reusable and transferable multicore technologies. Those were covered in the individual talks and plenum discussions. Beside that, working groups have been formed to discuss and present important topics in detail, which are also part of this report.
Cite as

Andreas Herkersdorf and Michael Paulitsch. Multicore Enablement for Embedded and Cyber Physical Systems (Dagstuhl Seminar 13052). In Dagstuhl Reports, Volume 3, Issue 1, pp. 149-182, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2013)

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@Article{herkersdorf_et_al:DagRep.3.1.149,
  author =	{Herkersdorf, Andreas and Paulitsch, Michael},
  title =	{{Multicore Enablement for Embedded and Cyber Physical Systems (Dagstuhl Seminar 13052)}},
  pages =	{149--182},
  journal =	{Dagstuhl Reports},
  ISSN =	{2192-5283},
  year =	{2013},
  volume =	{3},
  number =	{1},
  editor =	{Herkersdorf, Andreas and Paulitsch, Michael},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagRep.3.1.149},
  URN =		{urn:nbn:de:0030-drops-40155},
  doi =		{10.4230/DagRep.3.1.149},
  annote =	{Keywords: Multicore, hardware, software, platforms, embedded systems, security, real-time, safety, cyber physical systems}
}
Document
DOI: 10.4230/DagRep.1.5.1
Organic Computing - Design of Self-Organizing Systems (Dagstuhl Seminar 11181)

Authors: Kirstie Bellman, Andreas Herkersdorf, and Michael G. Hinchey

Published in: Dagstuhl Reports, Volume 1, Issue 5 (2011)

Abstract
This report documents the program and the outcomes of Dagstuhl Seminar 11181 ``Organic Computing - Design of Self-Organizing Systems''.
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Kirstie Bellman, Andreas Herkersdorf, and Michael G. Hinchey. Organic Computing - Design of Self-Organizing Systems (Dagstuhl Seminar 11181). In Dagstuhl Reports, Volume 1, Issue 5, pp. 1-28, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2011)

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@Article{bellman_et_al:DagRep.1.5.1,
  author =	{Bellman, Kirstie and Herkersdorf, Andreas and Hinchey, Michael G.},
  title =	{{Organic Computing - Design of Self-Organizing Systems (Dagstuhl Seminar 11181)}},
  pages =	{1--28},
  journal =	{Dagstuhl Reports},
  ISSN =	{2192-5283},
  year =	{2011},
  volume =	{1},
  number =	{5},
  editor =	{Bellman, Kirstie and Herkersdorf, Andreas and Hinchey, Michael G.},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagRep.1.5.1},
  URN =		{urn:nbn:de:0030-drops-32019},
  doi =		{10.4230/DagRep.1.5.1},
  annote =	{Keywords: Organic Computing, Self-Organization, Adaptivity, Trustworthy System Design}
}
Document
DOI: 10.4230/DagSemProc.06141.15
Reconfigurable Processing Units vs. Reconfigurable Interconnects

Authors: Andreas Herkersdorf, Christopher Claus, Michael Meitinger, Rainer Ohlendorf, and Thomas Wild

Published in: Dagstuhl Seminar Proceedings, Volume 6141, Dynamically Reconfigurable Architectures (2006)

Abstract
The question we proposed to explore with the seminar participants is whether the dynamic reconfigurable computing community is paying sufficient attention to the subject of dynamic reconfigurable SoC interconnects. By SoC interconnect, we refer to architecture- or system-level building blocks such as on-chip buses, crossbars, add-drop rings or meshed NoCs. P Our motivation to systematically investigate this question originates from conceptual and architectural challenges in the FlexPath project. FlexPath is a new Network Processor architecture that flexibly maps networking functions onto both SW programmable CPU resources and (re-)configurable HW building blocks in a way that different packet flows are forwarded via different, optimized processing paths. Packets with well defined processing requirements may even bypass the central CPU complex (AutoRoute). In consequence, CPU processing resources are more effectively used and the overall NP throughput is improved compared to conventional NPU architectures. P The following requirements apply with respect to the dynamic adaptation of the processing paths: The rule basis for NPU-internal processing path lookup is updated in the order of 100us, packet inter-arrival time is in the order of 100ns. Partial reconfiguration of the rule basis (and/or interconnect structure) with state of the art techniques would take several ms resulting in a continuously blocked system. However, performing path selection with conventional lookup table search and updates (and a statically configured on-chip bus) takes considerably less than 100ns. Hence, is there a need for new conceptual approaches with respect to dynamic SoC interconnect reconfiguration, or is this a ''no issue'' as conventional techniques are sufficient?
Cite as

Andreas Herkersdorf, Christopher Claus, Michael Meitinger, Rainer Ohlendorf, and Thomas Wild. Reconfigurable Processing Units vs. Reconfigurable Interconnects. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, pp. 1-3, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{herkersdorf_et_al:DagSemProc.06141.15,
  author =	{Herkersdorf, Andreas and Claus, Christopher and Meitinger, Michael and Ohlendorf, Rainer and Wild, Thomas},
  title =	{{Reconfigurable Processing Units vs. Reconfigurable Interconnects}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--3},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.15},
  URN =		{urn:nbn:de:0030-drops-7797},
  doi =		{10.4230/DagSemProc.06141.15},
  annote =	{Keywords: Reconfigurable SoC interconnect}
}
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