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Documents authored by Hruska, Tomas

Document
DOI: 10.4230/OASIcs.MEMICS.2010.47
Automatic C Compiler Generation from Architecture Description Language ISAC

Authors: Adam Husar, Miloslav Trmac, Jan Hranac, Tomas Hruska, and Karel Masarik

Published in: OASIcs, Volume 16, Sixth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS'10) -- Selected Papers (2011)

Abstract
This paper deals with retargetable compiler generation. After an introduction to application-specific instruction set processor design and a review of code generation in compiler backends, ISAC architecture description language is introduced. Automatic approach to instruction semantics extraction from ISAC models which result is usable for backend generation is presented. This approach was successfully tested on three models of MIPS, ARM and TI MSP430 architectures. Further backend generation process that uses extracted instruction is semantics presented. This process was currently tested on the MIPS architecture and some preliminary results are shown.
Cite as

Adam Husar, Miloslav Trmac, Jan Hranac, Tomas Hruska, and Karel Masarik. Automatic C Compiler Generation from Architecture Description Language ISAC. In Sixth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS'10) -- Selected Papers. Open Access Series in Informatics (OASIcs), Volume 16, pp. 47-53, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2011)

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@InProceedings{husar_et_al:OASIcs.MEMICS.2010.47,
  author =	{Husar, Adam and Trmac, Miloslav and Hranac, Jan and Hruska, Tomas and Masarik, Karel},
  title =	{{Automatic C Compiler Generation from Architecture Description Language ISAC}},
  booktitle =	{Sixth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS'10) -- Selected Papers},
  pages =	{47--53},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-22-4},
  ISSN =	{2190-6807},
  year =	{2011},
  volume =	{16},
  editor =	{Matyska, Ludek and Kozubek, Michal and Vojnar, Tomas and Zemcik, Pavel and Antos, David},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.MEMICS.2010.47},
  URN =		{urn:nbn:de:0030-drops-30654},
  doi =		{10.4230/OASIcs.MEMICS.2010.47},
  annote =	{Keywords: ISAC architecture, compiler generation}
}
Document
DOI: 10.4230/OASIcs.MEMICS.2010.93
Fast Translated Simulation of ASIPs

Authors: Zdenek Prikryl, Jakub Kroustek, Tomas Hruska, and Dusan Kolar

Published in: OASIcs, Volume 16, Sixth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS'10) -- Selected Papers (2011)

Abstract
Application-specific instruction set processors are the core of nowadays embedded systems. Therefore, the designers need to have powerful tools for the processor design. The tools should be generated automatically based on a processor description. One of the most important tools is the simulator. It is used during a testing phase of the processor design and during target software development. The key feature of the simulator is its speed. The concept of a special simulation type ­ translated simulation ­ is presented in this paper. This simulation exploits information from a target C compiler. Both the simulator and the C compiler are generated based on the processor description in an architecture description language ISAC. Experimental results of this concept show very good simulation speed and fast generation of the simulator.
Cite as

Zdenek Prikryl, Jakub Kroustek, Tomas Hruska, and Dusan Kolar. Fast Translated Simulation of ASIPs. In Sixth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS'10) -- Selected Papers. Open Access Series in Informatics (OASIcs), Volume 16, pp. 93-100, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2011)

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@InProceedings{prikryl_et_al:OASIcs.MEMICS.2010.93,
  author =	{Prikryl, Zdenek and Kroustek, Jakub and Hruska, Tomas and Kolar, Dusan},
  title =	{{Fast Translated Simulation of ASIPs}},
  booktitle =	{Sixth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS'10) -- Selected Papers},
  pages =	{93--100},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-22-4},
  ISSN =	{2190-6807},
  year =	{2011},
  volume =	{16},
  editor =	{Matyska, Ludek and Kozubek, Michal and Vojnar, Tomas and Zemcik, Pavel and Antos, David},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.MEMICS.2010.93},
  URN =		{urn:nbn:de:0030-drops-30608},
  doi =		{10.4230/OASIcs.MEMICS.2010.93},
  annote =	{Keywords: Hardware/sofware co-design, simulation, architecture description languages, application-specific instruction set processors}
}
Document
DOI: 10.4230/OASIcs.MEMICS.2010.109
Instructor Selector Generation from Architecture Description

Authors: Miloslav Trmac, Adam Husar, Jan Hranac, Tomas Hruska, and Karel Masarik

Published in: OASIcs, Volume 16, Sixth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS'10) -- Selected Papers (2011)

Abstract
We describe an automated way to generate data for a practical LLVM instruction selector based on machine-generated description of the target architecture at register transfer level. The generated instruction selector can handle arbitrarily complex machine instructions with no internal control flow, and can automatically find and take advantage of arithmetic properties of an instructions, specialized pseudo-registers and special cases of immediate operands.
Cite as

Miloslav Trmac, Adam Husar, Jan Hranac, Tomas Hruska, and Karel Masarik. Instructor Selector Generation from Architecture Description. In Sixth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS'10) -- Selected Papers. Open Access Series in Informatics (OASIcs), Volume 16, pp. 109-115, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2011)

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@InProceedings{trmac_et_al:OASIcs.MEMICS.2010.109,
  author =	{Trmac, Miloslav and Husar, Adam and Hranac, Jan and Hruska, Tomas and Masarik, Karel},
  title =	{{Instructor Selector Generation from Architecture Description}},
  booktitle =	{Sixth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS'10) -- Selected Papers},
  pages =	{109--115},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-22-4},
  ISSN =	{2190-6807},
  year =	{2011},
  volume =	{16},
  editor =	{Matyska, Ludek and Kozubek, Michal and Vojnar, Tomas and Zemcik, Pavel and Antos, David},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.MEMICS.2010.109},
  URN =		{urn:nbn:de:0030-drops-30616},
  doi =		{10.4230/OASIcs.MEMICS.2010.109},
  annote =	{Keywords: LLVM, instruction generator}
}
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