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Documents authored by Marwedel, Peter


Document
Evaluation of resource arbitration methods for multi-core real-time systems

Authors: Timon Kelter, Tim Harde, Peter Marwedel, and Heiko Falk

Published in: OASIcs, Volume 30, 13th International Workshop on Worst-Case Execution Time Analysis (2013)


Abstract
Multi-core systems have become prevalent in the last years, because of their favorable properties in terms of energy consumption, computing power and design complexity. First attempts have been made to devise WCET analyses for multi-core processors, which have to deal with the problem that the cores may experience interferences during accesses to shared resources. To limit these interferences, the vast amount of previous work is proposing a strict TDMA (time division multiple access) schedule for arbitrating shared resources. Though this type of arbitration yields a high predictability, this advantage is paid for with a poor resource utilization. In this work, we compare different arbitration methods with respect to their predictability and average case performance. We show how known WCET analysis techniques can be extended to work with the presented arbitration strategies and perform an evaluation of the resulting ACETs and WCETs on an extensive set of realworld benchmarks. Results show that there are cases when TDMA is not the best strategy, especially when predictability and performance are equally important.

Cite as

Timon Kelter, Tim Harde, Peter Marwedel, and Heiko Falk. Evaluation of resource arbitration methods for multi-core real-time systems. In 13th International Workshop on Worst-Case Execution Time Analysis. Open Access Series in Informatics (OASIcs), Volume 30, pp. 1-10, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2013)


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@InProceedings{kelter_et_al:OASIcs.WCET.2013.1,
  author =	{Kelter, Timon and Harde, Tim and Marwedel, Peter and Falk, Heiko},
  title =	{{Evaluation of resource arbitration methods for multi-core real-time systems}},
  booktitle =	{13th International Workshop on Worst-Case Execution Time Analysis},
  pages =	{1--10},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-54-5},
  ISSN =	{2190-6807},
  year =	{2013},
  volume =	{30},
  editor =	{Maiza, Claire},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2013.1},
  URN =		{urn:nbn:de:0030-drops-41173},
  doi =		{10.4230/OASIcs.WCET.2013.1},
  annote =	{Keywords: WCET analysis, multi-core, arbitration, shared resources}
}
Document
WCET-aware Software Based Cache Partitioning for Multi-Task Real-Time Systems

Authors: Sascha Plazar, Paul Lokuciejewski, and Peter Marwedel

Published in: OASIcs, Volume 10, 9th International Workshop on Worst-Case Execution Time Analysis (WCET'09) (2009)


Abstract
Caches are a source of unpredictability since it is very difficult to predict if a memory access results in a cache hit or miss. In systems running multiple tasks steered by a preempting scheduler, it is even impossible to determine the cache behavior since interrupt-driven schedulers lead to unknown points of time for context switches. Partitioned caches are already used in multi-task environments to increase the cache hit ratio by avoiding mutual eviction of tasks from the cache. For real-time systems, the upper bound of the execution time is one of the most important metrics, called the Worst-Case Execution Time (WCET). In this paper, we use partitioning of instruction caches as a technique to achieve tighter WCET estimations since tasks can not be evicted from their partition by other tasks. We propose a novel WCET-aware cache partitioning algorithm, which determines the optimal partition size for each task with focus on decreasing the system's WCET for a given set of possible partition sizes. Employing this algorithm, we are able to decrease the WCET depending on the number of tasks in a set by up to 34%. On average, reductions between 12% and 19% can be achieved.

Cite as

Sascha Plazar, Paul Lokuciejewski, and Peter Marwedel. WCET-aware Software Based Cache Partitioning for Multi-Task Real-Time Systems. In 9th International Workshop on Worst-Case Execution Time Analysis (WCET'09). Open Access Series in Informatics (OASIcs), Volume 10, pp. 1-11, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2009)


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@InProceedings{plazar_et_al:OASIcs.WCET.2009.2286,
  author =	{Plazar, Sascha and Lokuciejewski, Paul and Marwedel, Peter},
  title =	{{WCET-aware Software Based Cache Partitioning for Multi-Task Real-Time Systems}},
  booktitle =	{9th International Workshop on Worst-Case Execution Time Analysis (WCET'09)},
  pages =	{1--11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-14-9},
  ISSN =	{2190-6807},
  year =	{2009},
  volume =	{10},
  editor =	{Holsti, Niklas},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2009.2286},
  URN =		{urn:nbn:de:0030-drops-22860},
  doi =		{10.4230/OASIcs.WCET.2009.2286},
  annote =	{Keywords: WCET analysis, cache partitioning}
}
Document
Fast, predictable and low energy memory references through architecture-aware compilation

Authors: Peter Marwedel, Lars Wehmeyer, Manish Verma, Stefan Steinke, and Urs Helmig

Published in: Dagstuhl Seminar Proceedings, Volume 3471, Perspectives Workshop: Design of Systems with Predictable Behaviour (2004)


Abstract
The design of future high-performance embedded systems is hampered by two problems: First, the required hardware needs more energy than is available from batteries. Second, current cache-based approaches for bridging the increasing speed gap between processors and memories cannot guarantee predictable real-time behavior. A contribution to solving both problems is made in this paper which describes a comprehensive set of algorithms that can be applied at design time in order to maximally exploit scratch pad memories (SPMs). We show that both the energy consumption as well as the computed worst case execution time (WCET) can be reduced by up to to 80% and 48%, respectively, by establishing a strong link between the memory architecture and the compiler.

Cite as

Peter Marwedel, Lars Wehmeyer, Manish Verma, Stefan Steinke, and Urs Helmig. Fast, predictable and low energy memory references through architecture-aware compilation. In Perspectives Workshop: Design of Systems with Predictable Behaviour. Dagstuhl Seminar Proceedings, Volume 3471, pp. 1-16, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2004)


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@InProceedings{marwedel_et_al:DagSemProc.03471.3,
  author =	{Marwedel, Peter and Wehmeyer, Lars and Verma, Manish and Steinke, Stefan and Helmig, Urs},
  title =	{{Fast, predictable and low energy memory references through architecture-aware compilation}},
  booktitle =	{Perspectives Workshop: Design of Systems with Predictable Behaviour},
  pages =	{1--16},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2004},
  volume =	{3471},
  editor =	{Lothar Thiele and Reinhard Wilhelm},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.03471.3},
  URN =		{urn:nbn:de:0030-drops-66},
  doi =		{10.4230/DagSemProc.03471.3},
  annote =	{Keywords: Embedded system, compiler, energy efficiency, low power, WCET, scratchpad, memory access}
}
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