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Documents authored by Schaumont, Patrick

Document
DOI: 10.4230/DagRep.9.7.94
Secure Composition for Hardware Systems (Dagstuhl Seminar 19301)

Authors: Divya Arora, Ilia Polian, Francesco Regazzoni, and Patrick Schaumont

Published in: Dagstuhl Reports, Volume 9, Issue 7 (2020)

Abstract
The goal of the Dagstuhl Seminar 19301 ``Secure Composition for Hardware System'' was to establish a common understanding of principles and techniques that can facilitate composition and integration of hardware systems to achieve specified security guarantees. Theoretical foundations of secure composition have been laid out in the past, but they are limited to software systems. New and unique security challenges arise when a real system composed of a range of hardware components, including application-specific blocks, programmable microcontrollers, and reconfigurable fabrics, are put together. For example, these components may have different owners, different trust assumptions and may not even have a common language to describe their security properties to each other. Physical and side-channel attacks that take advantage of various physical properties to undermine a system's security objectives add another level of complexity to the secure composition problem. Moreover, practical hardware systems include software of tremendous size and complexity, and hardware-software interaction can create new security challenges. The seminar considered secure composition both from a pure hardware perspective, where multiple hardware blocks are composed in, e.g., a system on chip (SoC), and from a hardware-software perspective where hardware is integrated within a system that includes software. The seminar brought together researchers and industry practitioners from fields that have to deal with secure composition: Secure hardware architectures, hardware-oriented security, applied cryptography, test and verification of security properties. By involving industrial participants, we were able to get insights on real-world challenges, heuristics, and methodologies employed to address them and initiate a discussion towards new solutions.
Cite as

Divya Arora, Ilia Polian, Francesco Regazzoni, and Patrick Schaumont. Secure Composition for Hardware Systems (Dagstuhl Seminar 19301). In Dagstuhl Reports, Volume 9, Issue 7, pp. 94-116, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)

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@Article{arora_et_al:DagRep.9.7.94,
  author =	{Arora, Divya and Polian, Ilia and Regazzoni, Francesco and Schaumont, Patrick},
  title =	{{Secure Composition for Hardware Systems (Dagstuhl Seminar 19301)}},
  pages =	{94--116},
  journal =	{Dagstuhl Reports},
  ISSN =	{2192-5283},
  year =	{2019},
  volume =	{9},
  number =	{7},
  editor =	{Arora, Divya and Polian, Ilia and Regazzoni, Francesco and Schaumont, Patrick},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagRep.9.7.94},
  URN =		{urn:nbn:de:0030-drops-116377},
  doi =		{10.4230/DagRep.9.7.94},
  annote =	{Keywords: Hardware, Secure composition, Security, Software}
}
Document
DOI: 10.4230/DagRep.6.8.65
Foundations of Secure Scaling (Dagstuhl Seminar 16342)

Authors: Lejla Batina, Swarup Bhunia, Patrick Schaumont, and Jean-Pierre Seifert

Published in: Dagstuhl Reports, Volume 6, Issue 8 (2017)

Abstract
This report documents the program and the outcomes of Dagstuhl Seminar 16342 "Foundations of Secure Scaling". This seminar hosted researchers in secure electronic system design, spanning all abstraction levels from cryptographic engineering over chip design to system integration. We recognize that scaling is a fundamental force present at every abstraction level in electronic system design. While scaling is generally thought of as beneficial to the resulting implementations, this does not hold for secure electronic design. Indeed, the relations between scaling and the resulting security are poorly understood. This seminar facilitated the discussion between security experts at different abstraction levels in order to uncover the links between scaling and the resulting security.
Cite as

Lejla Batina, Swarup Bhunia, Patrick Schaumont, and Jean-Pierre Seifert. Foundations of Secure Scaling (Dagstuhl Seminar 16342). In Dagstuhl Reports, Volume 6, Issue 8, pp. 65-90, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)

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@Article{batina_et_al:DagRep.6.8.65,
  author =	{Batina, Lejla and Bhunia, Swarup and Schaumont, Patrick and Seifert, Jean-Pierre},
  title =	{{Foundations of Secure Scaling (Dagstuhl Seminar 16342)}},
  pages =	{65--90},
  journal =	{Dagstuhl Reports},
  ISSN =	{2192-5283},
  year =	{2017},
  volume =	{6},
  number =	{8},
  editor =	{Batina, Lejla and Bhunia, Swarup and Schaumont, Patrick and Seifert, Jean-Pierre},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagRep.6.8.65},
  URN =		{urn:nbn:de:0030-drops-68387},
  doi =		{10.4230/DagRep.6.8.65},
  annote =	{Keywords: Cryptographic Engineering, Very Large Scale Integration, Secure Hardware Design, Technology Scaling, Complexity Scaling, Secure Evaluation}
}
Document
DOI: 10.4230/DagSemProc.09282.5
Engineering On-Chip Thermal Effects

Authors: Patrick Schaumont

Published in: Dagstuhl Seminar Proceedings, Volume 9282, Foundations for Forgery-Resilient Cryptographic Hardware (2010)

Abstract
Temperature effects can be used to maliciously affect the behavior of digital crypto-circuits. For example, temperature effects can create covert communication channels, and they can affect the stability of physical unclonable functions (PUFs). This talk observes that these thermal effects can be engineered, and we describe two techniques. The first technique shows how to filter the information through a covert temperature channel. This leads to detectors for very specific events, for example, someone touching the chip package. The second technique shows how to mitigate the impact of temperature on a PUF design while avoiding costly post-processing. We discuss the design of a compact ring-oscillator PUF for FPGA which is tolerant to temperature variations.
Cite as

Patrick Schaumont. Engineering On-Chip Thermal Effects. In Foundations for Forgery-Resilient Cryptographic Hardware. Dagstuhl Seminar Proceedings, Volume 9282, pp. 1-2, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010)

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@InProceedings{schaumont:DagSemProc.09282.5,
  author =	{Schaumont, Patrick},
  title =	{{Engineering On-Chip Thermal Effects}},
  booktitle =	{Foundations for Forgery-Resilient Cryptographic Hardware},
  pages =	{1--2},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{9282},
  editor =	{Jorge Guajardo and Bart Preneel and Ahmad-Reza Sadeghi and Pim Tuyls},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.09282.5},
  URN =		{urn:nbn:de:0030-drops-24032},
  doi =		{10.4230/DagSemProc.09282.5},
  annote =	{Keywords: PUFs, temperature effects, covert temperature channel, ring oscillator PUF, FPGAs}
}
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