Methodologies for Designing Power-Aware Smart Card Systems

Abstract

Smart cards are some of the smallest 
computing platforms in use today. They have 
limited resources, but a huge number of 
functional requirements. The requirement for 
multi-application cards increases the demand 
for high performance and security even more, 
whereas the limits given by size and energy 
consumption remain constant. 

We describe  new 
methodologies for designing and implementing 
entire systems with regard to power awareness 
and required performance. To make use of this 
power-saving potential, also the higher layers 
of the system - the operating system layer and 
the application domain layer - are required to 
be designed together with the rest of the 
system.

HW/SW co-design methodologies enable the gain of 
system-level optimization. The first part  presents the 
abstraction of smart cards to optimize system architecture 
and memory system. Both functional and transactional-level 
models are presented and discussed. The proposed design 
flow and preliminary results of the evaluation are depicted.

Another central part of this methodology  is a cycle-accurate instruction-set
simulator for secure software development. 
The underlaying energy model is designed
to decouple instruction and data dependent energy dissipation,
which leads to an independent characterization process and allows
stepwise model refinement to increase estimation accuracy. The
model has been evaluated for a high-performance smart card CPU and
an use-case for secure software is given.