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System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric

Authors Vittoriano Muttillo , Vincenzo Stoico , Giacomo Valente , Marco Santic , Luigi Pomante , Daniele Frigioni

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Subject Classification

ACM Subject Classification
  • Computer systems organization → Embedded systems
  • Computer systems organization → Embedded hardware
Keywords
  • embedded systems
  • hw/sw co-design
  • performance estimation
  • lasso
  • machine learning

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Abstract

The rapidly increasing complexity of embedded systems and the critical impact of non-functional requirements demand the adoption of an appropriate system-level HW/SW co-design methodology. This methodology tries to satisfy all design requirements by simultaneously considering several alternative HW/SW implementations. In this context, early performance estimation approaches are crucial in reducing the design space, thereby minimizing design time and cost. To address the challenge of system-level performance estimation, this work presents and formalizes a novel approach based on a unifying HW/SW performance metric for early execution time estimation. The proposed approach estimates the execution time of a C function when executed by different HW/SW processor technologies. The approach is validated through an extensive experimental study, demonstrating its effectiveness and efficiency in terms of estimation error (i.e., lower than 10%) and estimation time (close to zero) when compared to existing methods in the literature.

Cite As Get BibTex

Vittoriano Muttillo, Vincenzo Stoico, Giacomo Valente, Marco Santic, Luigi Pomante, and Daniele Frigioni. System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric. In 16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2025). Open Access Series in Informatics (OASIcs), Volume 127, pp. 3:1-3:14, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2025) https://doi.org/10.4230/OASIcs.PARMA-DITAM.2025.3

Author Details

Vittoriano Muttillo
  • University of Teramo, Italy
Vincenzo Stoico
  • Vrije Universiteit Amsterdam, The Netherlands
Giacomo Valente
  • University of L’Aquila, Italy
Marco Santic
  • University of L’Aquila, Italy
Luigi Pomante
  • University of L’Aquila, Italy
Daniele Frigioni
  • University of L’Aquila, Italy

Funding

This research work has been funded by the Electronic Components and Systems for European Leadership Joint Undertaking (ECSEL JU) through the project AIDOaRt, grant agreement No. 101007350, and the Key Digital Technologies Joint Undertaking (KDT JU) through the project MATISSE, grant agreement No. 101140216.

Supplementary Materials

References

  1. Vikas Agrawal, Anand Pande, and Mahesh M. Mehendale. High level synthesis of multi-precision data flow graphs. In VLSI Design 2001. Fourteenth International Conference on VLSI Design, pages 411-416, 2001. URL: https://doi.org/10.1109/ICVD.2001.902693.
  2. Abderaouf Nassim Amalou, Elisa Fromont, and Isabelle Puaut. Fast and accurate context-aware basic block timing prediction using transformers. In Proceedings of the 33rd ACM SIGPLAN International Conference on Compiler Construction, CC 2024, pages 227-237, New York, NY, USA, 2024. Association for Computing Machinery. URL: https://doi.org/10.1145/3640537.3641572.
  3. Yunsheng Bai, Atefeh Sohrabizadeh, Zongyue Qin, Ziniu Hu, Yizhou Sun, and Jason Cong. Towards a comprehensive benchmark for high-level synthesis targeted to fpgas. In Proceedings of the 37th International Conference on Neural Information Processing Systems, NIPS '23, Red Hook, NY, USA, 2024. Curran Associates Inc. Google Scholar
  4. Carlo Brandolese, William Fornaciari, Luigi Pomante, Fabio Salice, and Donatella Sciuto. Affinity-driven system design exploration for heterogeneous multiprocessor soc. IEEE Transactions on Computers, 55(5):508-519, May 2006. URL: https://doi.org/10.1109/TC.2006.66.
  5. Carlo Brandolese, William Fornaciari, Fabio Salice, and Donatella Sciuto. Source-level execution time estimation of c programs. In Proceedings of the Ninth International Symposium on Hardware/Software Codesign, pages 98-103, New York, NY, USA, 2001. Association for Computing Machinery. URL: https://doi.org/10.1145/371636.371694.
  6. Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason H. Anderson, Stephen Brown, and Tomasz Czajkowski. Legup: high-level synthesis for fpga-based processor/accelerator systems. In Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '11, pages 33-36, New York, NY, USA, 2011. Association for Computing Machinery. URL: https://doi.org/10.1145/1950413.1950423.
  7. Steve Dai, Yuan Zhou, Hang Zhang, Ecenur Ustun, Evangeline F.Y. Young, and Zhiru Zhang. Fast and accurate estimation of quality of results in high-level synthesis with machine learning. In 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pages 129-132, 2018. URL: https://doi.org/10.1109/FCCM.2018.00029.
  8. P. Derler, E. A. Lee, and A. Sangiovanni Vincentelli. Modeling cyber–physical systems. Proceedings of the IEEE, 100(1):13-28, 2012. Google Scholar
  9. Tania Di Mascio, Luigi Laura, and Marco Temperini. A framework for personalized competitive programming training. In 2018 17th International Conference on Information Technology Based Higher Education and Training (ITHET), pages 1-8, 2018. URL: https://doi.org/10.1109/ITHET.2018.8424620.
  10. Daniele Di Pompeo, Emilio Incerto, Vittoriano Muttillo, Luigi Pomante, and Giacomo Valenete. An efficient performance-driven approach for hw/sw co-design. In Proceedings of the 8th ACM/SPEC on International Conference on Performance Engineering, ICPE '17, pages 323-326, New York, NY, USA, 2017. Association for Computing Machinery. URL: https://doi.org/10.1145/3030207.3030239.
  11. Christof Ebert and Capers Jones. Embedded software: Facts, figures, and future. Computer, 42(4):42-52, 2009. URL: https://doi.org/10.1109/MC.2009.118.
  12. Paolo Giammatteo, Federico Vincenzo Fiordigigli, Luigi Pomante, Tania Di Mascio, and Federica Caruso. Age & gender classifier for edge computing. In 2019 8th Mediterranean Conference on Embedded Computing (MECO), pages 1-4, 2019. URL: https://doi.org/10.1109/MECO.2019.8760160.
  13. José Andrés Jiménez, José Amelio Medina Merodio, and Luis Fernández Sanz. Checklists for compliance to do-178c and do-278a standards. Computer Standards & Interfaces, 52:41-50, 2017. URL: https://doi.org/10.1016/j.csi.2017.01.006.
  14. Marco Lattuada and Fabrizio Ferrandi. Performance modeling of embedded applications with zero architectural knowledge. In 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 277-286, 2010. URL: https://doi.org/10.1145/1878961.1879010.
  15. Hosein Mohammadi Makrani, Hossein Sayadi, Tinoosh Mohsenin, Setareh rafatirad, Avesta Sasan, and Houman Homayoun. Xppe: Cross-platform performance estimation of hardware accelerators using machine learning. In ASPDAC '19, ASPDAC '19, pages 727-732, New York, NY, USA, 2019. Association for Computing Machinery. URL: https://doi.org/10.1145/3287624.3288756.
  16. Dimosthenis Masouros, Aggelos Ferikoglou, Georgios Zervakis, Sotirios Xydis, and Dimitrios Soudris. Late breaking results: Language-level qor modeling for high-level synthesis. In Proceedings of the 61st ACM/IEEE Design Automation Conference, DAC '24, New York, NY, USA, 2024. Association for Computing Machinery. URL: https://doi.org/10.1145/3649329.3663500.
  17. Hosein Mohammadi Makrani, Farnoud Farahmand, Hossein Sayadi, Sara Bondi, Sai Manoj Pudukotai Dinakarrao, Houman Homayoun, and Setareh Rafatirad. Pyramid: Machine learning framework to estimate the optimal timing and resource usage of a high-level synthesis design. In 2019 29th International Conference on Field Programmable Logic and Applications (FPL), pages 397-403, 2019. URL: https://doi.org/10.1109/FPL.2019.00069.
  18. Vittoriano Muttillo, Claudio Di Sipio, Riccardo Rubei, Luca Berardinelli, and MohammadHadi Dehghani. Towards synthetic trace generation of modeling operations using in-context learning approach. In Proceedings of the 39th IEEE/ACM International Conference on Automated Software Engineering, ASE '24, pages 619-630, New York, NY, USA, 2024. Association for Computing Machinery. URL: https://doi.org/10.1145/3691620.3695058.
  19. Vittoriano Muttillo, Paolo Giammatteo, and Vincenzo Stoico. Statement-level timing estimation for embedded system design using machine learning techniques. In Proceedings of the ACM/SPEC International Conference on Performance Engineering, ICPE '21, pages 257-264, New York, NY, USA, 2021. Association for Computing Machinery. URL: https://doi.org/10.1145/3427921.3450258.
  20. Vittoriano Muttillo, Paolo Giammatteo, Vincenzo Stoico, and Luigi Pomante. An early-stage statement-level metric for energy characterization of embedded processors. Microprocessors and Microsystems, 77:103200, 2020. URL: https://doi.org/10.1016/J.MICPRO.2020.103200.
  21. Vittoriano Muttillo, Luigi Pomante, Marco Santic, and Giacomo Valente. Systemc-based co-simulation/analysis for system-level hardware/software co-design. Computers and Electrical Engineering, 110:108803, 2023. URL: https://doi.org/10.1016/j.compeleceng.2023.108803.
  22. Vittoriano Muttillo and Vincenzo Stoico. SLIDE-x (System-Level Infrastructure for HW/SW Dataset E-xtraction). Software, version 1.0., swhId: https://archive.softwareheritage.org/swh:1:rev:0907cf39f7d023d0dc2e8307e1ffef6115d0377a;origin=https://github.com/hepsycode/SLIDE-x;visit=swh:1:snp:d73c612114afc6dff6a86a042fa006576440f5ec (visited on 2025-02-12). URL: https://github.com/hepsycode/SLIDE-x, URL: https://doi.org/10.4230/artifacts.22912.
  23. Vittoriano Muttillo, Vincenzo Stoico, Marco Santic, Giacomo Valente, Luigi Pomante, and Daniele Frigioni. Slide-x-ml: System-level infrastructure for dataset e-xtraction and machine learning framework for high-level synthesis estimations. In 2024 IEEE 42nd International Conference on Computer Design (ICCD), pages 616-619, 2024. URL: https://doi.org/10.1109/ICCD63220.2024.00098.
  24. Vittoriano Muttillo, Giacomo Valente, Daniele Ciambrone, Vincenzo Stoico, and Luigi Pomante. Hepsycode-rt: a real-time extension for an esl hw/sw co-design methodology. In Proceedings of the Rapido'18 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, RAPIDO '18, New York, NY, USA, 2018. Association for Computing Machinery. URL: https://doi.org/10.1145/3180665.3180670.
  25. Vittoriano Muttillo, Giacomo Valente, Fabio Federici, Luigi Pomante, Marco Faccio, Carlo Tieri, and Serenella Ferri. A design methodology for soft-core platforms on fpga with smp linux, openmp support, and distributed hardware profiling system. Eurasip Journal on Embedded Systems, 2016(1), 2017. URL: https://doi.org/10.1186/s13639-016-0051-9.
  26. Vittoriano Muttillo, Giacomo Valente, Luigi Pomante, Vincenzo Stoico, Fausto D’Antonio, and Fabio Salice. Cc4cs: An off-the-shelf unifying statement-level performance metric for hw/sw technologies. In Companion of the 2018 ACM/SPEC International Conference on Performance Engineering, ICPE ’18, pages 119-122, New York, NY, USA, 2018. Association for Computing Machinery. URL: https://doi.org/10.1145/3185768.3186291.
  27. Razvan Nane, Vlad-Mihai Sima, Christian Pilato, Jongsok Choi, Blair Fort, Andrew Canis, Yu Ting Chen, Hsuan Hsiao, Stephen Brown, Fabrizio Ferrandi, Jason Anderson, and Koen Bertels. A survey and evaluation of fpga high-level synthesis tools. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35(10):1591-1604, October 2016. URL: https://doi.org/10.1109/TCAD.2015.2513673.
  28. Kenneth O'Neal, Mitch Liu, Hans Tang, Amin Kalantar, Kennen DeRenard, and Philip Brisk. Hlspredict: Cross platform performance prediction for fpga high-level synthesis. In 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 1-8, 2018. URL: https://doi.org/10.1145/3240765.3240816.
  29. Jürgen Teich. Hardware/software codesign: The past, the present, and predicting the future. Proceedings of the IEEE, 100(Special Centennial Issue):1411-1430, 2012. URL: https://doi.org/10.1109/JPROC.2011.2182009.
  30. Walter Tiberti, Federica Caruso, Luigi Pomante, Marco Pugliese, Marco Santic, and Fortunato Santucci. Development of an extended topology-based lightweight cryptographic scheme for ieee 802.15.4 wireless sensor networks. International Journal of Distributed Sensor Networks, 16(10):1550147720951673, 2020. URL: https://doi.org/10.1177/1550147720951673.
  31. Giacomo Valente, Gianluca Brilli, Tania Di Mascio, Alessandro Capotondi, Paolo Burgio, Paolo Valente, and Andrea Marongiu. Fine-grained qos control via tightly-coupled bandwidth monitoring and regulation for fpga-based heterogeneous socs. IEEE Transactions on Parallel and Distributed Systems, pages 1-15, 2024. URL: https://doi.org/10.1109/TPDS.2024.3513416.
  32. Giacomo Valente, Tiziana Fanni, Carlo Sau, Tania Di Mascio, Luigi Pomante, and Francesca Palumbo. A composable monitoring system for heterogeneous embedded platforms. ACM Trans. Embed. Comput. Syst., 20(5), July 2021. URL: https://doi.org/10.1145/3461647.
  33. R. Valentini, P.D. Marco, R. Alesii, and F. Santucci. Cross-layer analysis of multi-static rfid systems exploiting capture diversity. IEEE Transactions on Communications, 69(10):6620-6632, 2021. URL: https://doi.org/10.1109/TCOMM.2021.3096541.
  34. Weiyan Zhang, Mehran Goli, and Rolf Drechsler. Early performance estimation of embedded software on risc-v processor using linear regression. In 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 20-25, 2022. URL: https://doi.org/10.1109/DDECS54261.2022.9770144.
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