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System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric

Authors Vittoriano Muttillo , Vincenzo Stoico , Giacomo Valente , Marco Santic , Luigi Pomante , Daniele Frigioni

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Author Details

Vittoriano Muttillo
  • University of Teramo, Italy
Vincenzo Stoico
  • Vrije Universiteit Amsterdam, The Netherlands
Giacomo Valente
  • University of L’Aquila, Italy
Marco Santic
  • University of L’Aquila, Italy
Luigi Pomante
  • University of L’Aquila, Italy
Daniele Frigioni
  • University of L’Aquila, Italy

Funding

This research work has been funded by the Electronic Components and Systems for European Leadership Joint Undertaking (ECSEL JU) through the project AIDOaRt, grant agreement No. 101007350, and the Key Digital Technologies Joint Undertaking (KDT JU) through the project MATISSE, grant agreement No. 101140216.

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Vittoriano Muttillo, Vincenzo Stoico, Giacomo Valente, Marco Santic, Luigi Pomante, and Daniele Frigioni. System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric. In 16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2025). Open Access Series in Informatics (OASIcs), Volume 127, pp. 3:1-3:14, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2025) https://doi.org/10.4230/OASIcs.PARMA-DITAM.2025.3

Abstract

The rapidly increasing complexity of embedded systems and the critical impact of non-functional requirements demand the adoption of an appropriate system-level HW/SW co-design methodology. This methodology tries to satisfy all design requirements by simultaneously considering several alternative HW/SW implementations. In this context, early performance estimation approaches are crucial in reducing the design space, thereby minimizing design time and cost. To address the challenge of system-level performance estimation, this work presents and formalizes a novel approach based on a unifying HW/SW performance metric for early execution time estimation. The proposed approach estimates the execution time of a C function when executed by different HW/SW processor technologies. The approach is validated through an extensive experimental study, demonstrating its effectiveness and efficiency in terms of estimation error (i.e., lower than 10%) and estimation time (close to zero) when compared to existing methods in the literature.

Subject Classification

ACM Subject Classification
  • Computer systems organization → Embedded systems
  • Computer systems organization → Embedded hardware
Keywords
  • embedded systems
  • hw/sw co-design
  • performance estimation
  • lasso
  • machine learning

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References

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