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Leibniz Transactions on Embedded Systems, Volume 4, Issue 2
LITES, Volume 4, Issue 2
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LITES, Volume 4
Journal: Leibniz Transactions on Embedded Systems (LITES)
Publication Details
- published at: 2017-07-07
- Publisher: Schloss Dagstuhl – Leibniz-Zentrum für Informatik
- DBLP: db/journals/lites/lites4
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Complete Issue
LITES, Volume 4, Issue 2
Abstract
LITES, Volume 4, Issue 2
Cite as
LITES, Volume 4, Issue 2, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@Article{LITES-v004-i002,
title = {{LITES, Volume 4, Issue 2}},
journal = {Leibniz Transactions on Embedded Systems},
ISSN = {2199-2002},
year = {2017},
volume = {4},
number = {2},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v004-i002},
doi = {10.4230/LITES-v004-i002},
annote = {Keywords: LITES, Volume 4, Issue 2}
}
Document
Dynamic and Static Task Allocation for Hard Real-Time Video Stream Decoding on NoCs
Abstract
Hard real-time (HRT) video systems require admission control decisions that rely on two factors. Firstly, schedulability analysis of the data-dependent, communicating tasks within the application need to be carried out in order to guarantee timing and predictability. Secondly, the allocation of the tasks to multi-core processing elements would generate different results in the schedulability analysis. Due to the conservative nature of the state-of-the-art schedulability analysis of tasks and message flows, and the unpredictability in the application, the system resources are often under-utilised. In this paper we propose two blocking-aware dynamic task allocation techniques that exploit application and platform characteristics, in order to increase the number of simultaneous, fully schedulable, video streams handled by the system. A novel, worst-case response time aware, search-based, static hard real-time task mapper is introduced to act as an upper-baseline to the proposed techniques. Further evaluations are carried out against existing heuristic-based dynamic mappers. Improvements to the admission rates and the system utilisation under a range of different workloads and platform sizes are explored.
Cite as
Hashan R. Mendis, Neil C. Audsley, and Leandro Soares Indrusiak. Dynamic and Static Task Allocation for Hard Real-Time Video Stream Decoding on NoCs. In LITES, Volume 4, Issue 2 (2017). Leibniz Transactions on Embedded Systems, Volume 4, Issue 2, pp. 01:1-01:25, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@Article{mendis_et_al:LITES-v004-i002-a001,
author = {Mendis, Hashan R. and Audsley, Neil C. and Indrusiak, Leandro Soares},
title = {{Dynamic and Static Task Allocation for Hard Real-Time Video Stream Decoding on NoCs}},
journal = {Leibniz Transactions on Embedded Systems},
pages = {01:1--01:25},
ISSN = {2199-2002},
year = {2017},
volume = {4},
number = {2},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v004-i002-a001},
URN = {urn:nbn:de:0030-drops-192689},
doi = {10.4230/LITES-v004-i002-a001},
annote = {Keywords: Real-time multimedia, Task mapping, Network-on-chip}
}
Document
EMSBench: Benchmark and Testbed for Reactive Real-Time Systems
Abstract
Benchmark suites for real-time embedded systems (RTES) usually contain only pure computations that are often used in this domain. They allow to evaluate computing performance, but do not reproduce the complexity and behaviour that is typical for such systems. Actual RTES have to interact with the physical environment, which is often reflected by code that is executed concurrently. In this article, we present the software package EMSBench that mimics such complex behaviour, and highlight some of its use cases. The benchmark code ems of EMSBench is based on the open-source engine management system (EMS) FreeEMS. Additionally, EMSBench contains a trace generator (tg) that provides input signals for ems and enables to execute ems close to reality. We provide detailed descriptions of the ems's execution behaviour and of trace generation. EMSBench can be used as test or benchmark program to compare different hardware platforms, e.g. in terms of schedulability. Also, we use EMSBench as a benchmark for static worst-case execution time (WCET) analysis and compare these results to measurements performed on existing hardware. Our results based on the OTAWA WCET estimation tool show WCET overestimations by the static analysis from 11.9% to 41.1% depending on the complexity of the analysed functions.
Cite as
Florian Kluge, Christine Rochange, and Theo Ungerer. EMSBench: Benchmark and Testbed for Reactive Real-Time Systems. In LITES, Volume 4, Issue 2 (2017). Leibniz Transactions on Embedded Systems, Volume 4, Issue 2, pp. 02:1-02:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)
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@Article{kluge_et_al:LITES-v004-i002-a002,
author = {Kluge, Florian and Rochange, Christine and Ungerer, Theo},
title = {{EMSBench: Benchmark and Testbed for Reactive Real-Time Systems}},
journal = {Leibniz Transactions on Embedded Systems},
pages = {02:1--02:23},
ISSN = {2199-2002},
year = {2017},
volume = {4},
number = {2},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v004-i002-a002},
URN = {urn:nbn:de:0030-drops-192698},
doi = {10.4230/LITES-v004-i002-a002},
annote = {Keywords: Real-time benchmark, WCET Analysis, Engine Management System}
}
Document
Per Processor Spin-Based Protocols for Multiprocessor Real-Time Systems
Abstract
This paper investigates preemptive spin-based global resource sharing protocols for resource-constrained real-time embedded multi-core systems based on partitioned fixed-priority preemptive scheduling. We present preemptive spin-based protocols that feature (i) an increased schedulability ratio of task sets and reduced response jitter of tasks compared to the classical non-preemptive spin-based protocol, (ii) similar memory requirements for the administration of waiting tasks as for the non-preemptive protocol whilst only causing (iii) a minimal increase of the minimal number of required stacks per core from one to at most two, and (iv) strong progress guarantees to tasks. We complement these protocols with a unified worst-case response time analysis that specializes to the classical analysis for the non-preemptive protocol. The paper includes a comparative evaluation of the preemptive protocols and the non-preemptive protocol based on synthetic data.
Cite as
Sara Afshar, Moris Behnam, Reinder J. Bril, and Thomas Nolte. Per Processor Spin-Based Protocols for Multiprocessor Real-Time Systems. In LITES, Volume 4, Issue 2 (2017). Leibniz Transactions on Embedded Systems, Volume 4, Issue 2, pp. 03:1-03:30, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018)
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@Article{afshar_et_al:LITES-v004-i002-a003,
author = {Afshar, Sara and Behnam, Moris and Bril, Reinder J. and Nolte, Thomas},
title = {{Per Processor Spin-Based Protocols for Multiprocessor Real-Time Systems}},
journal = {Leibniz Transactions on Embedded Systems},
pages = {03:1--03:30},
ISSN = {2199-2002},
year = {2018},
volume = {4},
number = {2},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v004-i002-a003},
URN = {urn:nbn:de:0030-drops-192708},
doi = {10.4230/LITES-v004-i002-a003},
annote = {Keywords: Resource sharing, Real-time systems, Multiprocessors, Spin-locks}
}