Volume

Dagstuhl Seminar Proceedings, Volume 7041



Publication Details

  • published at: 2007-07-30
  • Publisher: Schloss-Dagstuhl - Leibniz Zentrum für Informatik

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Document
07041 Abstracts Collection – Power-aware Computing Systems

Authors: Luca Benini, Naehyuck Chang, Ulrich Kremer, and Christian W. Probst


Abstract
From January 21, 2007 to January 26, 2007, the Dagstuhl Seminar 07041``Power-aware Computing Systems'' was held in the International Conference and Research Center (IBFI), Schloss Dagstuhl. During the seminar, several participants presented their current research, and discussed ongoing work and open problems. This report compiles abstracts of the seminar presentations as well as the seminar results and ideas, providing hyperlinks to full papers wherever possible.

Cite as

Luca Benini, Naehyuck Chang, Ulrich Kremer, and Christian W. Probst. 07041 Abstracts Collection – Power-aware Computing Systems. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 7041, pp. 1-14, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2007)


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@InProceedings{benini_et_al:DagSemProc.07041.1,
  author =	{Benini, Luca and Chang, Naehyuck and Kremer, Ulrich and Probst, Christian W.},
  title =	{{07041 Abstracts Collection – Power-aware Computing Systems}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--14},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2007},
  volume =	{7041},
  editor =	{Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.07041.1},
  URN =		{urn:nbn:de:0030-drops-11248},
  doi =		{10.4230/DagSemProc.07041.1},
  annote =	{Keywords: Power consumption, energy reduction, compilers, microarchitectures, simulations, experimental frameworks}
}
Document
07041 Summary – Power-aware Computing Systems

Authors: Luca Benini, Naehyuck Chang, Ulrich Kremer, and Christian W. Probst


Abstract
The program of the Dagstuhl seminar 07041 on Power-aware Computing Systems featured presentations of about 25 participating researchers from academia and industry. They were chosen to represent major areas in targeting the energy consumption of a computing system – Applications, Compilers, Virtual-execution Environments, Operating Systems, and Hardware. In order to continue the work of the predecessor Dagstuhl seminar held in 2005, the results of that seminar [1] were discussed, with the aim of developing a vision of challenges, problems, and research activities in some of the key areas identified in 2005. The first part of the seminar was dedicated to lively discussions that led to the identification of three areas that were considered being most interesting. As a result, three groups were formed to further identify challenges and opportunities. The results of these groups are presented in this report. In addition, abstracts of the presentations as well as work-in-progress papers are published in these proceedings.

Cite as

Luca Benini, Naehyuck Chang, Ulrich Kremer, and Christian W. Probst. 07041 Summary – Power-aware Computing Systems. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 7041, pp. 1-7, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2007)


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@InProceedings{benini_et_al:DagSemProc.07041.2,
  author =	{Benini, Luca and Chang, Naehyuck and Kremer, Ulrich and Probst, Christian W.},
  title =	{{07041 Summary – Power-aware Computing Systems}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--7},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2007},
  volume =	{7041},
  editor =	{Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.07041.2},
  URN =		{urn:nbn:de:0030-drops-11232},
  doi =		{10.4230/DagSemProc.07041.2},
  annote =	{Keywords: Power-aware Computing Systems, Low-power Design, Parallelism and Power Consumption}
}
Document
07041 Working Group – Towards Interfaces for Integrated Performance and Power Analysis and Simulation

Authors: Chris Bleakley, Tom Clerckx, Harald Devos, Matthias Grumer, Alex Janek, Ulrich Kremer, Christian W. Probst, Phillip Stanley-Marbell, Christian Steger, Vasanth Venkatachalam, and Manuel Wendt


Abstract
In the design and optimization of power-aware computing systems, it is often desired to estimate power consumption at various levels of abstraction, e.g., at the transistor, gate, RTL, behavioral or transaction levels. Tools for power estimation at these different levels of abstraction require specialized expertise, e.g., understanding of device physics for circuit-level power estimation, and as such are necessarily developed by different research communities. In the optimization of complete platforms however, it is desired to be able to obtain aggregate power and performance estimates for the different components of a system, and this requires the ability to model the system at a mixture of levels of abstraction. One approach to enabling such cross-abstraction modeling, is to define a mechanism for interchange of data between tools at different layers of abstraction, for both static analysis and simulation-based studies. This document presents preliminary discussions on the requirements of such an interface.

Cite as

Chris Bleakley, Tom Clerckx, Harald Devos, Matthias Grumer, Alex Janek, Ulrich Kremer, Christian W. Probst, Phillip Stanley-Marbell, Christian Steger, Vasanth Venkatachalam, and Manuel Wendt. 07041 Working Group – Towards Interfaces for Integrated Performance and Power Analysis and Simulation. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 7041, pp. 1-6, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2007)


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@InProceedings{bleakley_et_al:DagSemProc.07041.3,
  author =	{Bleakley, Chris and Clerckx, Tom and Devos, Harald and Grumer, Matthias and Janek, Alex and Kremer, Ulrich and Probst, Christian W. and Stanley-Marbell, Phillip and Steger, Christian and Venkatachalam, Vasanth and Wendt, Manuel},
  title =	{{07041 Working Group – Towards Interfaces for Integrated Performance and Power Analysis and Simulation}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--6},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2007},
  volume =	{7041},
  editor =	{Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.07041.3},
  URN =		{urn:nbn:de:0030-drops-11072},
  doi =		{10.4230/DagSemProc.07041.3},
  annote =	{Keywords: Power Estimation Tools, Simulation, Tool Interfaces}
}
Document
Automist - A Tool for Automated Instruction Set Characterization of Embedded Processors

Authors: Manuel Wendt, Matthias Grumer, Christian Steger, and Ulrich Neffe


Abstract
The steadily increasing performance of mobile devices also implies a rise in power consumption. To counteract this trend it is mandatory to accomplish software power optimizations based on accurate power consumption models characterized for the processor. This paper presents an environment for automated instruction set characterization based on physical power measurements. Based on a detailed instruction set description a testbench generator creates all needed test programs for a complete characterization. Afterwards those programs are executed by the processor and the energy consumption is measured. For an accurate energy measurement a high performance sampling technique has been established, which can be either clock or energy driven.

Cite as

Manuel Wendt, Matthias Grumer, Christian Steger, and Ulrich Neffe. Automist - A Tool for Automated Instruction Set Characterization of Embedded Processors. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 7041, pp. 1-10, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2007)


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@InProceedings{wendt_et_al:DagSemProc.07041.4,
  author =	{Wendt, Manuel and Grumer, Matthias and Steger, Christian and Neffe, Ulrich},
  title =	{{Automist - A Tool for Automated Instruction Set Characterization of Embedded Processors}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--10},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2007},
  volume =	{7041},
  editor =	{Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.07041.4},
  URN =		{urn:nbn:de:0030-drops-11097},
  doi =		{10.4230/DagSemProc.07041.4},
  annote =	{Keywords: Software energy estimation, automated processor characterization, testbench generator, current measurement, clock driven sampling, energy driven sampl}
}
Document
Compiler-based Software Power Peak Elimination on Smart Card Systems

Authors: Matthias Grumer, Manuel Wendt, Christian Steger, Reinhold Weiss, Ulrich Neffe, and Andreas Muehlberger


Abstract
RF-powered smart cards are widely used in different application areas today. For smart cards not only performance is an important attribute, but also the power consumed by a given application. The power consumed is heavily depending on the software executed on the system. The power profile, especially the power peaks, of an executed application influence the system stability and security. Flattening the power profile can thus increase the stability and security of a system. In this paper we present an optimization system that allows a reduction of power peaks based on a compiler optimization. The optimizations are done on different levels of the compiler. In the backend of the compiler we present new instruction scheduling algorithms. On the intermediate language level we propose the use of iterative compiling for reducing critical peaks.

Cite as

Matthias Grumer, Manuel Wendt, Christian Steger, Reinhold Weiss, Ulrich Neffe, and Andreas Muehlberger. Compiler-based Software Power Peak Elimination on Smart Card Systems. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 7041, pp. 1-9, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2007)


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@InProceedings{grumer_et_al:DagSemProc.07041.5,
  author =	{Grumer, Matthias and Wendt, Manuel and Steger, Christian and Weiss, Reinhold and Neffe, Ulrich and Muehlberger, Andreas},
  title =	{{Compiler-based Software Power Peak Elimination on Smart Card Systems}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--9},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2007},
  volume =	{7041},
  editor =	{Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.07041.5},
  URN =		{urn:nbn:de:0030-drops-11030},
  doi =		{10.4230/DagSemProc.07041.5},
  annote =	{Keywords: Software power optimization, compiler optimization, peak reduction}
}
Document
Complexity of Scheduling in Synthesizing Hardware from Concurrent Action Oriented Specifications

Authors: Gaurav Singh, S. S. Ravi, Sumit Ahuja, and Sandeep Shukla


Abstract
Concurrent Action Oriented Specifications (CAOS) formalism such as Bluespec Inc.'s Bluespec System Verilog (BSV) has been recently shown to be effective for hardware modeling and synthesis. This formalism offers the benefits of automatic handling of concurrency issues in highly concurrent system descriptions, and the associated synthesis algorithms have been shown to produce efficient hardware comparable to those generated from hand-written Verilog/VHDL. These benefits which are inherent in such a synthesis process also aid in faster architectural exploration. This is because CAOS allows a high-level description (above RTL) of a design in terms of atomic transactions, where each transaction corresponds to a collection of operations. Optimal scheduling of such actions in CAOS-based synthesis process is crucial in order to generate hardware that is efficient in terms of area, latency and power. In this paper, we analyze the complexity of the scheduling problems associated with CAOS-based synthesis and discuss several heuristics for meeting the peak power goals of designs generated from CAOS. We also discuss approximability of these problems as appropriate.

Cite as

Gaurav Singh, S. S. Ravi, Sumit Ahuja, and Sandeep Shukla. Complexity of Scheduling in Synthesizing Hardware from Concurrent Action Oriented Specifications. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 7041, pp. 1-25, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2007)


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@InProceedings{singh_et_al:DagSemProc.07041.6,
  author =	{Singh, Gaurav and Ravi, S. S. and Ahuja, Sumit and Shukla, Sandeep},
  title =	{{Complexity of Scheduling in Synthesizing Hardware from Concurrent Action Oriented Specifications}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--25},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2007},
  volume =	{7041},
  editor =	{Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.07041.6},
  URN =		{urn:nbn:de:0030-drops-11055},
  doi =		{10.4230/DagSemProc.07041.6},
  annote =	{Keywords: Hardware Synthesis, Concurrent Action Oriented Specifications (CAOS), Scheduling, Complexity, Peak Power.}
}
Document
Electrocardiogram on Wireless Sensor Nodes

Authors: Lennart Yseboodt, Michael De Nil, and Mladen Berekovic


Abstract
Wireless sensor nodes are applicable in a wide range of situations such as the medical, industrial or environmental domains, but the focus is on the biomedical domain. This paper presents the steps taken to develop a low power processor using Silicon Hive technology and mapping an electrocardiogram analysis algorithm on that processor. Today's energy-scavengers are able to deliver 100microwatt. This is the global power constraint of the sensor node. With a total power consumption of 16microwatt, the DSP processes the samples, compresses them into extracted parameters and the results are sent out by means of a radio.

Cite as

Lennart Yseboodt, Michael De Nil, and Mladen Berekovic. Electrocardiogram on Wireless Sensor Nodes. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 7041, pp. 1-4, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2007)


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@InProceedings{yseboodt_et_al:DagSemProc.07041.7,
  author =	{Yseboodt, Lennart and De Nil, Michael and Berekovic, Mladen},
  title =	{{Electrocardiogram on Wireless Sensor Nodes}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--4},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2007},
  volume =	{7041},
  editor =	{Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.07041.7},
  URN =		{urn:nbn:de:0030-drops-11118},
  doi =		{10.4230/DagSemProc.07041.7},
  annote =	{Keywords: Ultra-low-power, electrocardiogram, wireless}
}
Document
Energy Scalability and the RESUME Scalable Video Codec

Authors: Harald Devos, Hendrik Eeckhaut, Mark Christiaens, and Dirk Stroobandt


Abstract
In the context of the RESUME-project a scalable wavelet-based video decoder was built to demonstrate the benefits of reconfigurable hardware for scalable applications. emph{Scalable} video means that the quality of service (QoS), i.e., the frame rate, resolution, color depth, ldots of the decoded video can easily be changed by only decoding those parts of the video stream that contribute to the desired QoS. With the emergence of high-performance FPGAs (Field Programmable Gate Array), both the required performance for real-time decoding and flexibility, by allowing reconfiguration, are offered. Since the amount of calculations scales with the QoS, energy dissipation is expected to scale similarly. To investigate the relation between QoS and energy dissipation we actually measured the energy dissipation of a scalable video decoder implementation on a FPGA. The measurements show how dissipation effectively scales with the QoS, but also depends on the decoded data and the used design method. This is illustrated by comparing two different implementations of the inverse discrete wavelet transform (IDWT).

Cite as

Harald Devos, Hendrik Eeckhaut, Mark Christiaens, and Dirk Stroobandt. Energy Scalability and the RESUME Scalable Video Codec. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 7041, pp. 1-12, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2007)


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@InProceedings{devos_et_al:DagSemProc.07041.8,
  author =	{Devos, Harald and Eeckhaut, Hendrik and Christiaens, Mark and Stroobandt, Dirk},
  title =	{{Energy Scalability and the RESUME Scalable Video Codec}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--12},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2007},
  volume =	{7041},
  editor =	{Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.07041.8},
  URN =		{urn:nbn:de:0030-drops-11120},
  doi =		{10.4230/DagSemProc.07041.8},
  annote =	{Keywords: Wavelet-based Scalable Video, Energy Measurement, Hardware Generation, FPGA}
}
Document
Lifetime Extension of Higher Class UHF RFID Tags using special Power Management Techniques and Energy Harvesting Devices

Authors: Alex Janek, Christian Steger, Josef Preishuber-Pfluegl, and Markus Pistauer


Abstract
Enhanced RFID tag technology especially in the UHF frequency range provides extended functionality like high operating range and sensing and monitoring capabilities. Such functionality requiring extended system structures including data acquisition units, real time clocks and active transmitters causes a high energy consumption of the tag and requires an on board energy store (battery). As a key parameter of the reliability of an RFID system is the lifetime, the energy budget of the higher class tag has to be as balanced as possible. This can be achieved by using energy harvesting devices as additional power supply. The PowerTag project and thus this paper proposes special power management mechanisms in combination with special energy storage structures interfacing energy harvesting devices and dealing with their special requirements. First various power management and power saving techniques are simulated and their performance is evaluated. In a second step different implementation variants of energy storage structures are compared by using accurate simulation models of the various parts of the system. The results are compared to manufacturer given and guaranteed system performance parameters of a state-of-the-art higher class UHF RFID system. The presented approach combines two simulations for the design and the evaluation of different tag architectures and power saving techniques. Simulation results are showing an improvement of over 44\% of achievable lifetime applying the power saving techniques and power subsystem architectures presented in this paper, compared to a state-of-the-art higher class system.

Cite as

Alex Janek, Christian Steger, Josef Preishuber-Pfluegl, and Markus Pistauer. Lifetime Extension of Higher Class UHF RFID Tags using special Power Management Techniques and Energy Harvesting Devices. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 7041, pp. 1-20, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2007)


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@InProceedings{janek_et_al:DagSemProc.07041.9,
  author =	{Janek, Alex and Steger, Christian and Preishuber-Pfluegl, Josef and Pistauer, Markus},
  title =	{{Lifetime Extension of Higher Class UHF RFID Tags using special Power Management Techniques and Energy Harvesting Devices}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--20},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2007},
  volume =	{7041},
  editor =	{Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.07041.9},
  URN =		{urn:nbn:de:0030-drops-11041},
  doi =		{10.4230/DagSemProc.07041.9},
  annote =	{Keywords: Higher Class UHF RFID, Energy harvesting, Energy storage architectures, Lifetime extension}
}
Document
The Sunflower Tool Suite --- Hardware and Software Research Platforms for Energy-Constrained and Failure-Prone Systems

Authors: Phillip Stanley-Marbell


Abstract
Research in any field requires tools that enable modeling system characteristics of interest. Such tools, whether analytic, simulative, or hardware-based, must enable the accurate evaluation of relevant aspects of a system that may influence its perceived utility. In computing systems research, software tools (notably, simulators) provide low-cost, flexible, and low turn-around time facilities for investigations, but abstract away many hardware details, often resulting in a loss in accuracy of modeling. Hardware implementations provide the ultimate proofs of concept, but require hardware design expertise, are usually expensive and inflexible, and are not always designed to expose all possible system parameters to researchers. They are also rarely the subject of active evolution over time as research platforms in their own right, as software tools are. The Sunflower tool suite is a suite of hardware platforms and simulation tools, intended to address these concerns. It comprises a full-system (embedded microarchitecture, networking, power, battery, device failure and analog signal modeling) simulator, a miniature energy-scavenging hardware platform, and a handheld computing device (under development). The suite is intended to provide a set of complementary platforms for research in micro- and system-architectures for embedded systems, with emphases on energy-efficiency, fault-tolerance, and ecological impact of deployed hardware.

Cite as

Phillip Stanley-Marbell. The Sunflower Tool Suite --- Hardware and Software Research Platforms for Energy-Constrained and Failure-Prone Systems. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 7041, pp. 1-3, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2007)


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@InProceedings{stanleymarbell:DagSemProc.07041.10,
  author =	{Stanley-Marbell, Phillip},
  title =	{{The Sunflower Tool Suite --- Hardware and Software Research Platforms for Energy-Constrained and Failure-Prone Systems}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--3},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2007},
  volume =	{7041},
  editor =	{Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.07041.10},
  URN =		{urn:nbn:de:0030-drops-11069},
  doi =		{10.4230/DagSemProc.07041.10},
  annote =	{Keywords: Research Platforms, Hardware Prototypes, Microarchitectural Simulation, Energy Harvesting/Scavenging, Sensor Networks.}
}
Document
Thermal Characterization and Thermal Management in Processor-Based Systems

Authors: José Luis Ayala, Anya Apavatjrut, David Atienza, Marisa López-Vallejo, and Carlos A. López-Barrio


Abstract
The register file is one of the hottest devices in processor-based systems. Leakage reduction techniques and DTM mechanisms require a thermal characterization of the hardware. This paper presents a thermal model to analyze the temperature evolution in the shared register files found on VLIW systems. The use of this model allows the analysis of several factors that have an strong impact on the heat transfer. The results obtained can be used in the design of temperature-aware compilers and place&route tools.

Cite as

José Luis Ayala, Anya Apavatjrut, David Atienza, Marisa López-Vallejo, and Carlos A. López-Barrio. Thermal Characterization and Thermal Management in Processor-Based Systems. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 7041, pp. 1-10, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2007)


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@InProceedings{ayala_et_al:DagSemProc.07041.11,
  author =	{Ayala, Jos\'{e} Luis and Apavatjrut, Anya and Atienza, David and L\'{o}pez-Vallejo, Marisa and L\'{o}pez-Barrio, Carlos A.},
  title =	{{Thermal Characterization and Thermal Management in Processor-Based Systems}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--10},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2007},
  volume =	{7041},
  editor =	{Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.07041.11},
  URN =		{urn:nbn:de:0030-drops-11103},
  doi =		{10.4230/DagSemProc.07041.11},
  annote =	{Keywords: Thermal characterization, thermal model, register file}
}
Document
Towards Class-Based Dynamic Voltage Scaling for Multimedia Applications

Authors: Richard Urunuela, Gilles Muller, and Julia Lawall


Abstract
Video display has significant, but highly variable, CPU requirements. As such, it is an attractive target for power management via dynamic voltage scaling. In previous work, we have proposed a dynamic voltage scaling algorithm directed to the context of video kiosks, in which a minimal frequency for each frame can be determined experimentally based on observations taken during the first few iterations of the video. In this paper, we review that work, and begin to consider how such an approach can be adapted to the more common case where a video is only played once, on hardware that is not known in advance.

Cite as

Richard Urunuela, Gilles Muller, and Julia Lawall. Towards Class-Based Dynamic Voltage Scaling for Multimedia Applications. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 7041, pp. 1-8, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2007)


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@InProceedings{urunuela_et_al:DagSemProc.07041.12,
  author =	{Urunuela, Richard and Muller, Gilles and Lawall, Julia},
  title =	{{Towards Class-Based Dynamic Voltage Scaling for Multimedia Applications}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--8},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2007},
  volume =	{7041},
  editor =	{Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.07041.12},
  URN =		{urn:nbn:de:0030-drops-11088},
  doi =		{10.4230/DagSemProc.07041.12},
  annote =	{Keywords: Dynamic voltage scaling, multimedia applications, embedded systems}
}

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