Volume
OASIcs, Volume 87
Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021)
-
Part of:
Series:
Open Access Series in Informatics (OASIcs)
Conference: Workshop on Next Generation Real-Time Embedded Systems (NG-RES)
Event
NG-RES 2021, January 20, 2021, Budapest, HungaryEditors
Publication Details
- published at: 2021-01-14
- Publisher: Schloss Dagstuhl – Leibniz-Zentrum für Informatik
- ISBN: 978-3-95977-178-8
- DBLP: db/conf/hipeac/ngres2021
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Document
Complete Volume
OASIcs, Volume 87, NG-RES 2021, Complete Volume
Abstract
OASIcs, Volume 87, NG-RES 2021, Complete Volume
Cite as
Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021). Open Access Series in Informatics (OASIcs), Volume 87, pp. 1-74, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2021)
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@Proceedings{bertogna_et_al:OASIcs.NG-RES.2021,
title = {{OASIcs, Volume 87, NG-RES 2021, Complete Volume}},
booktitle = {Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021)},
pages = {1--74},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-178-8},
ISSN = {2190-6807},
year = {2021},
volume = {87},
editor = {Bertogna, Marko and Terraneo, Federico},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2021},
URN = {urn:nbn:de:0030-drops-134757},
doi = {10.4230/OASIcs.NG-RES.2021},
annote = {Keywords: OASIcs, Volume 87, NG-RES 2021, Complete Volume}
}
Document
Front Matter
Front Matter, Table of Contents, Preface, Conference Organization
Abstract
Front Matter, Table of Contents, Preface, Conference Organization
Cite as
Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021). Open Access Series in Informatics (OASIcs), Volume 87, pp. 0:i-0:x, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2021)
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@InProceedings{bertogna_et_al:OASIcs.NG-RES.2021.0,
author = {Bertogna, Marko and Terraneo, Federico},
title = {{Front Matter, Table of Contents, Preface, Conference Organization}},
booktitle = {Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021)},
pages = {0:i--0:x},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-178-8},
ISSN = {2190-6807},
year = {2021},
volume = {87},
editor = {Bertogna, Marko and Terraneo, Federico},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2021.0},
URN = {urn:nbn:de:0030-drops-134767},
doi = {10.4230/OASIcs.NG-RES.2021.0},
annote = {Keywords: Front Matter, Table of Contents, Preface, Conference Organization}
}
Document
Invited Paper
A Comparative Evaluation of Latency-Aware Energy Optimization Approaches in Many-Core Systems (Invited Paper)
Abstract
Many applications vary a lot in execution time depending on their workload. A prominent example is image processing applications, where the execution time is dependent on the content or the size of the processed input images. An interesting case is when these applications have quality-of-service requirements such as soft deadlines, that they should meet as good as possible. A further complicated case is when such applications have one or even multiple further objectives to optimize like, e.g., energy consumption.
Approaches that dynamically adapt the processing resources to application needs under multiple optimization goals and constraints can be characterized into the application-specific and feedback-based techniques. Whereas application-specific approaches typically statically use an offline stage to determine the best configuration for each known workload, feedback-based approaches, using, e.g., control theory, adapt the system without the need of knowing the effect of workload on these goals.
In this paper, we evaluate a state-of-the-art approach of each of the two categories and compare them for image processing applications in terms of energy consumption and number of deadline misses on a given many-core architecture. In addition, we propose a second feedback-based approach that is based on finite state machines (FSMs). The obtained results suggest that whereas the state-of-the-art application-specific approach is able to meet a specified latency deadline whenever possible while consuming the least amount of energy, it requires a perfect characterization of the workload on a given many-core system. If such knowledge is not available, the feedback-based approaches have their strengths in achieving comparable energy savings, but missing deadlines more often.
Cite as
Khalil Esper, Stefan Wildermann, and Jürgen Teich. A Comparative Evaluation of Latency-Aware Energy Optimization Approaches in Many-Core Systems (Invited Paper). In Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021). Open Access Series in Informatics (OASIcs), Volume 87, pp. 1:1-1:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2021)
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@InProceedings{esper_et_al:OASIcs.NG-RES.2021.1,
author = {Esper, Khalil and Wildermann, Stefan and Teich, J\"{u}rgen},
title = {{A Comparative Evaluation of Latency-Aware Energy Optimization Approaches in Many-Core Systems}},
booktitle = {Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021)},
pages = {1:1--1:12},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-178-8},
ISSN = {2190-6807},
year = {2021},
volume = {87},
editor = {Bertogna, Marko and Terraneo, Federico},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2021.1},
URN = {urn:nbn:de:0030-drops-134779},
doi = {10.4230/OASIcs.NG-RES.2021.1},
annote = {Keywords: energy optimization, control-theory, timing analysis, soft real-time, dynamic voltage and frequency scaling, finite state machines, multi-core, many-core}
}
Document
EDF Scheduling and Minimal-Overlap Shortest-Path Routing for Real-Time TSCH Networks
Abstract
With the scope of Industry 4.0 and the Industrial Internet of Things (IIoT), wireless technologies have gained momentum in the industrial realm. Wireless standards such as WirelessHART, ISA100.11a, IEEE 802.15.4e and 6TiSCH are among the most popular, given their suitability to support real-time data traffic in wireless sensor and actuator networks (WSAN). Theoretical and empirical studies have covered prioritized packet scheduling in extenso, but only little has been done concerning methods that enhance and/or guarantee real-time performance based on routing decisions. In this work, we propose a greedy heuristic to reduce overlap in shortest-path routing for WSANs with packet transmissions scheduled under the earliest-deadline-first (EDF) policy. We evaluated our approach under varying network configurations and observed remarkable dominance in terms of the number of overlaps, transmission conflicts, and schedulability, regardless of the network workload and connectivity. We further observe that well-known graph network parameters, e.g., vertex degree, density, betweenness centrality, etc., have a special influence on the path overlaps, and thus provide useful insights to improve the real-time performance of the network.
Cite as
Miguel Gutiérrez Gaitán, Luís Almeida, Pedro Miguel Santos, and Patrick Meumeu Yomsi. EDF Scheduling and Minimal-Overlap Shortest-Path Routing for Real-Time TSCH Networks. In Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021). Open Access Series in Informatics (OASIcs), Volume 87, pp. 2:1-2:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2021)
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@InProceedings{gaitan_et_al:OASIcs.NG-RES.2021.2,
author = {Gait\'{a}n, Miguel Guti\'{e}rrez and Almeida, Lu{\'\i}s and Santos, Pedro Miguel and Yomsi, Patrick Meumeu},
title = {{EDF Scheduling and Minimal-Overlap Shortest-Path Routing for Real-Time TSCH Networks}},
booktitle = {Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021)},
pages = {2:1--2:12},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-178-8},
ISSN = {2190-6807},
year = {2021},
volume = {87},
editor = {Bertogna, Marko and Terraneo, Federico},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2021.2},
URN = {urn:nbn:de:0030-drops-134786},
doi = {10.4230/OASIcs.NG-RES.2021.2},
annote = {Keywords: Real-time communication, Routing, Scheduling, TDMA, Wireless networks}
}
Document
Static Allocation of Basic Blocks Based on Runtime and Memory Requirements in Embedded Real-Time Systems with Hierarchical Memory Layout
Abstract
Modern microcontrollers for safety-critical real-time systems use a hierarchical memory system to increase execution speed and memory capacity. For this purpose, flash memories, which offer high capacity at low transfer rates, are combined with scratchpad memories, which provide high access speed at low memory capacities. The main goal is to use both types of memory in such a way that their advantages are optimally exploited. The target is to allocate runtime-intensive code fragments with low memory requirements to the fast scratchpad memories. Previous approaches to separate program code on system memories consider the executed functions as the smallest logical unit. This is contradicted by the fact that not all parts of a function have the same computing time in relation to their memory usage. This article introduces a procedure that automatically analyses the compiled source code and identifies runtime intensive fragments. For this purpose, the translated code is executed in an offline simulator and the maximum repetition for each instruction is detected. This information is used to create logical code fragments called basic blocks. This is repeated for all functions in the overall system. During the analysis of the functions, the dependencies between them are also extracted and a corresponding call-graph with the call frequencies is generated. By combining the information from the call graph and the evaluation of the basic blocks, a prognosis of the computing load of the respective code blocks is created, which serves as base for the distribution into the fast scratchpad memories. To verify the described procedure, EEMBC’s CoreMark is executed on an Infineon AURIX TC29x microcontroller, in which different scratchpad sizes are simulated. It is demonstrated that the allocation of basic blocks scales significantly better with smaller memory sizes than the previous function-based approach.
Cite as
Philipp Jungklass and Mladen Berekovic. Static Allocation of Basic Blocks Based on Runtime and Memory Requirements in Embedded Real-Time Systems with Hierarchical Memory Layout. In Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021). Open Access Series in Informatics (OASIcs), Volume 87, pp. 3:1-3:14, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2021)
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@InProceedings{jungklass_et_al:OASIcs.NG-RES.2021.3,
author = {Jungklass, Philipp and Berekovic, Mladen},
title = {{Static Allocation of Basic Blocks Based on Runtime and Memory Requirements in Embedded Real-Time Systems with Hierarchical Memory Layout}},
booktitle = {Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021)},
pages = {3:1--3:14},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-178-8},
ISSN = {2190-6807},
year = {2021},
volume = {87},
editor = {Bertogna, Marko and Terraneo, Federico},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2021.3},
URN = {urn:nbn:de:0030-drops-134790},
doi = {10.4230/OASIcs.NG-RES.2021.3},
annote = {Keywords: Memory Architecture, Memory Management, Real-time Systems}
}
Document
Event-Based Control Enters the Real-Time World: Perspectives and Pitfalls
Abstract
In the last years, event-based control techniques have been gaining a steadily increasing importance owing to the advantages they bring, such as reduced network traffic, low actuator wear, reduced energy consumption of the involved devices. Applying the event-based paradigm in the context of real-time control opens up new opportunities, but introduces new challenges as well. In this paper we provide an overview of both opportunities and challenges, outlining the major problems to be tackled and as a consequence future research directions.
Cite as
Silvano Seva, William Fornaciari, and Alberto Leva. Event-Based Control Enters the Real-Time World: Perspectives and Pitfalls. In Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021). Open Access Series in Informatics (OASIcs), Volume 87, pp. 4:1-4:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2021)
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@InProceedings{seva_et_al:OASIcs.NG-RES.2021.4,
author = {Seva, Silvano and Fornaciari, William and Leva, Alberto},
title = {{Event-Based Control Enters the Real-Time World: Perspectives and Pitfalls}},
booktitle = {Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021)},
pages = {4:1--4:11},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-178-8},
ISSN = {2190-6807},
year = {2021},
volume = {87},
editor = {Bertogna, Marko and Terraneo, Federico},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2021.4},
URN = {urn:nbn:de:0030-drops-134803},
doi = {10.4230/OASIcs.NG-RES.2021.4},
annote = {Keywords: Real-time control, Wireless control, Event-based control, Cyber-physical systems, Industrial control networks, Industry 4.0}
}
Document
M2OS-Mc: An RTOS for Many-Core Processors
Abstract
A current trend of industrial systems is reducing space, weight and power (SWaP) through the allocation of different applications on a single chip. This is enabled by the continued improvement of semiconductor technology which allows the integration of multiple cores in a single processor chip, as the processors are prevented to continue increasing their clock rate due to the "power-wall". The use of Commercial-Off-The-Shelf (COTS) multi-core processors for real-time purposes presents issues due to the shared bus used to access the shared memory. An alternative to the use of multi-core processors are the many-core processors with tens to hundreds of processors in the same chip, using different scalable ways to interconnect their cores. This paper presents the adaptation of the M2OS Real-Time Operating System (RTOS) and its simplified Ada run-time for mesh-based many-core processors. This RTOS is called M2OS-mc and has been tested on the Epiphany III many-core processor (referred in this paper simply as Epiphany), a many-core which has 16 cores connected by a Network-on-Chip (NoC) consisting of a 4x4 2D mesh. In order to have a synchronized way to send messages between tasks through the NoC independently of the core where they are being executed, we provide sampling port communication primitives.
Cite as
David García Villaescusa, Mario Aldea Rivas, and Michael González Harbour. M2OS-Mc: An RTOS for Many-Core Processors. In Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021). Open Access Series in Informatics (OASIcs), Volume 87, pp. 5:1-5:13, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2021)
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@InProceedings{villaescusa_et_al:OASIcs.NG-RES.2021.5,
author = {Villaescusa, David Garc{\'\i}a and Rivas, Mario Aldea and Harbour, Michael Gonz\'{a}lez},
title = {{M2OS-Mc: An RTOS for Many-Core Processors}},
booktitle = {Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021)},
pages = {5:1--5:13},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-178-8},
ISSN = {2190-6807},
year = {2021},
volume = {87},
editor = {Bertogna, Marko and Terraneo, Federico},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2021.5},
URN = {urn:nbn:de:0030-drops-134814},
doi = {10.4230/OASIcs.NG-RES.2021.5},
annote = {Keywords: M2OS, Many-Core, Real-Time, Parallella, Epiphany, Network-on-Chip, Operating System, RTOS}
}