Write-back caches are a popular choice in embedded microprocessors as they promise higher performance than write-through caches. So far, however, their use in hard real-time systems has been prohibited by the lack of adequate worst-case execution time (WCET) analysis support. In this paper, we introduce a new approach to statically analyze the behavior of write-back caches. Prior work took an "eviction-focussed perspective", answering for each potential cache miss: May this miss evict a dirty cache line and thus cause a write back? We complement this approach by exploring a "store-focussed perspective", answering for each store: May this store dirtify a clean cache line and thus cause a write back later on? Experimental evaluation demonstrates substantial precision improvements when both perspectives are combined. For most benchmarks, write-back caches are then preferable to write-through caches in terms of the computed WCET bounds.
@InProceedings{bla_et_al:LIPIcs.ECRTS.2017.26, author = {Bla{\ss}, Tobias and Hahn, Sebastian and Reineke, Jan}, title = {{Write-Back Caches in WCET Analysis}}, booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)}, pages = {26:1--26:22}, series = {Leibniz International Proceedings in Informatics (LIPIcs)}, ISBN = {978-3-95977-037-8}, ISSN = {1868-8969}, year = {2017}, volume = {76}, editor = {Bertogna, Marko}, publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik}, address = {Dagstuhl, Germany}, URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.26}, URN = {urn:nbn:de:0030-drops-71589}, doi = {10.4230/LIPIcs.ECRTS.2017.26}, annote = {Keywords: write-back caches, real-time systems, WCET analysis, cache analysis} }
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