pdf-format: |
|
|
artifact-format: |
|
@Article{sensfelder_et_al:DARTS:2019:10735, author = {Nathana{\"e}l Sensfelder and Julien Brunel and Claire Pagetti}, title = {{Modeling Cache Coherence to Expose Interference (Artifact)}}, pages = {7:1--7:2}, journal = {Dagstuhl Artifacts Series}, ISSN = {2509-8195}, year = {2019}, volume = {5}, number = {1}, publisher = {Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik}, address = {Dagstuhl, Germany}, URL = {http://drops.dagstuhl.de/opus/volltexte/2019/10735}, URN = {urn:nbn:de:0030-drops-107358}, doi = {10.4230/DARTS.5.1.7}, annote = {Keywords: Real-time systems, multi-core processor, cache coherence, formal methods} }
Keywords: | Real-time systems, multi-core processor, cache coherence, formal methods | |
Seminar: | Special Issue of the 31st Euromicro Conference on Real-Time Systems (ECRTS 2019) | |
Related Scholarly Article: | https://dx.doi.org/10.4230/LIPIcs.ECRTS.2019.18 | |
Issue date: | 2019 | |
Date of publication: | 08.07.2019 |