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Documents authored by Derrien, Steven

Document
DOI: 10.4230/LIPIcs.ECRTS.2026.14
WCET Analysis of HLS-Generated Processors Using Abstract Interpretation

Authors: Thomas Feuilletin, Dylan Leothaud, Simon Rokicki, Steven Derrien, and Isabelle Puaut

Published in: LIPIcs, Volume 375, 38th European Conference on Real-Time Systems (ECRTS 2026)

Abstract
Deriving sound and precise timing models remains one of the main obstacles to static Worst-Case Execution Time (WCET) analysis. Modern processors exhibit diverse and evolving microarchitectures, making manual construction of timing models labor-intensive, error-prone, and difficult to adapt across processor variants. High-Level Synthesis (HLS) enables rapid customization of processor cores and architectural exploration, offering an opportunity to automate not only hardware generation but also the derivation of associated timing models. This paper presents an automated WCET analysis for HLS-generated processors based on abstract interpretation. We exploit the internal Gated-SSA representation of the HLS flow to automatically extract an abstract timing model capturing speculation and stall mechanisms. WCET estimation at the basic block level is then formulated as an exploration of abstract microarchitectural states within a basic block. The approach safely accounts for timing anomalies, while remaining scalable thanks to an efficient state-merging strategy. Integrated into the Heptane WCET tool and evaluated on Mälardalen benchmarks and a RISC-V, the method achieves the same tightness as a handcrafted timing model, while improving over a previously proposed automated approach.
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Thomas Feuilletin, Dylan Leothaud, Simon Rokicki, Steven Derrien, and Isabelle Puaut. WCET Analysis of HLS-Generated Processors Using Abstract Interpretation. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 14:1-14:19, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)

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@InProceedings{feuilletin_et_al:LIPIcs.ECRTS.2026.14,
  author =	{Feuilletin, Thomas and Leothaud, Dylan and Rokicki, Simon and Derrien, Steven and Puaut, Isabelle},
  title =	{{WCET Analysis of HLS-Generated Processors Using Abstract Interpretation}},
  booktitle =	{38th European Conference on Real-Time Systems (ECRTS 2026)},
  pages =	{14:1--14:19},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-429-1},
  ISSN =	{1868-8969},
  year =	{2026},
  volume =	{375},
  editor =	{Kritikakou, Angeliki},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.14},
  URN =		{urn:nbn:de:0030-drops-266069},
  doi =		{10.4230/LIPIcs.ECRTS.2026.14},
  annote =	{Keywords: Static Analysis, Worst-Case Execution Time, High-Level Synthesis}
}
Document
DOI: 10.4230/LIPIcs.ECRTS.2019.25
Hiding Communication Delays in Contention-Free Execution for SPM-Based Multi-Core Architectures

Authors: Benjamin Rouxel, Stefanos Skalistis, Steven Derrien, and Isabelle Puaut

Published in: LIPIcs, Volume 133, 31st Euromicro Conference on Real-Time Systems (ECRTS 2019)

Abstract
Multi-core systems using ScratchPad Memories (SPMs) are attractive architectures for executing time-critical embedded applications, because they provide both predictability and performance. In this paper, we propose a scheduling technique that jointly selects SPM contents off-line, in such a way that the cost of SPM loading/unloading is hidden. Communications are fragmented to augment hiding possibilities. Experimental results show the effectiveness of the proposed technique on streaming applications and synthetic task-graphs. The overlapping of communications with computations allows the length of generated schedules to be reduced by 4% on average on streaming applications, with a maximum of 16%, and by 8% on average for synthetic task graphs. We further show on a case study that generated schedules can be implemented with low overhead on a predictable multi-core architecture (Kalray MPPA).
Cite as

Benjamin Rouxel, Stefanos Skalistis, Steven Derrien, and Isabelle Puaut. Hiding Communication Delays in Contention-Free Execution for SPM-Based Multi-Core Architectures. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 25:1-25:24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)

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@InProceedings{rouxel_et_al:LIPIcs.ECRTS.2019.25,
  author =	{Rouxel, Benjamin and Skalistis, Stefanos and Derrien, Steven and Puaut, Isabelle},
  title =	{{Hiding Communication Delays in Contention-Free Execution for SPM-Based Multi-Core Architectures}},
  booktitle =	{31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
  pages =	{25:1--25:24},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-110-8},
  ISSN =	{1868-8969},
  year =	{2019},
  volume =	{133},
  editor =	{Quinton, Sophie},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.25},
  URN =		{urn:nbn:de:0030-drops-107626},
  doi =		{10.4230/LIPIcs.ECRTS.2019.25},
  annote =	{Keywords: Real-time Systems, Contention-Free Scheduling, SPM multi-core architecture}
}
Document
DOI: 10.4230/OASIcs.WCET.2018.9
Fine-Grain Iterative Compilation for WCET Estimation

Authors: Isabelle Puaut, Mickaël Dardaillon, Christoph Cullmann, Gernot Gebhard, and Steven Derrien

Published in: OASIcs, Volume 63, 18th International Workshop on Worst-Case Execution Time Analysis (WCET 2018)

Abstract
Compiler optimizations, although reducing the execution times of programs, raise issues in static WCET estimation techniques and tools. Flow facts, such as loop bounds, may not be automatically found by static WCET analysis tools after aggressive code optimizations. In this paper, we explore the use of iterative compilation (WCET-directed program optimization to explore the optimization space), with the objective to (i) allow flow facts to be automatically found and (ii) select optimizations that result in the lowest WCET estimates. We also explore to which extent code outlining helps, by allowing the selection of different optimization options for different code snippets of the application.
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Isabelle Puaut, Mickaël Dardaillon, Christoph Cullmann, Gernot Gebhard, and Steven Derrien. Fine-Grain Iterative Compilation for WCET Estimation. In 18th International Workshop on Worst-Case Execution Time Analysis (WCET 2018). Open Access Series in Informatics (OASIcs), Volume 63, pp. 9:1-9:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018)

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@InProceedings{puaut_et_al:OASIcs.WCET.2018.9,
  author =	{Puaut, Isabelle and Dardaillon, Micka\"{e}l and Cullmann, Christoph and Gebhard, Gernot and Derrien, Steven},
  title =	{{Fine-Grain Iterative Compilation for WCET Estimation}},
  booktitle =	{18th International Workshop on Worst-Case Execution Time Analysis (WCET 2018)},
  pages =	{9:1--9:12},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-073-6},
  ISSN =	{2190-6807},
  year =	{2018},
  volume =	{63},
  editor =	{Brandner, Florian},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2018.9},
  URN =		{urn:nbn:de:0030-drops-97556},
  doi =		{10.4230/OASIcs.WCET.2018.9},
  annote =	{Keywords: Worst-Case Execution Time Estimation, Compiler optimizations, Iterative Compilation, Flow fact extraction, Outlining}
}
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