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DOI: 10.4230/OASIcs.WCET.2005.813

Analysis of Memory Latencies in Multi-Processor Systems

Authors: Jan Stachulat, Simon Schliecker, Matthias Ivers, and Rolf Ernst

Published in: OASIcs, Volume 1, 5th International Workshop on Worst-Case Execution Time Analysis (WCET'05) (2007)

Abstract

Predicting timing behavior is key to efficient embedded real-time system design and verification. Current approaches to determine end-to-end latencies in parallel heterogeneous architectures focus on performance analysis either on task or system level. Especially memory accesses, basic operations of embedded application, cannot be accurately captured on a single level alone: While task level methods simplify system behavior, system level methods simplify task behavior. Both perspectives lead to overly pessimistic estimations. To tackle these complex interactions we integrate task and system level analysis. Each analysis level is provided with the necessary data to allow precise computations, while adequate abstraction prevents high time complexity.

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Jan Stachulat, Simon Schliecker, Matthias Ivers, and Rolf Ernst. Analysis of Memory Latencies in Multi-Processor Systems. In 5th International Workshop on Worst-Case Execution Time Analysis (WCET'05). Open Access Series in Informatics (OASIcs), Volume 1, pp. 33-36, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2007)

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@InProceedings{stachulat_et_al:OASIcs.WCET.2005.813,
  author =	{Stachulat, Jan and Schliecker, Simon and Ivers, Matthias and Ernst, Rolf},
  title =	{{Analysis of Memory Latencies in Multi-Processor Systems}},
  booktitle =	{5th International Workshop on Worst-Case Execution Time Analysis (WCET'05)},
  pages =	{33--36},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-24-8},
  ISSN =	{2190-6807},
  year =	{2007},
  volume =	{1},
  editor =	{Wilhelm, Reinhard},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2005.813},
  URN =		{urn:nbn:de:0030-drops-8130},
  doi =		{10.4230/OASIcs.WCET.2005.813},
  annote =	{Keywords: Multi-processor Performance Analysis, Memory Access Latency, Worst Case Execution Time}
}

Document

DOI: 10.4230/OASIcs.WCET.2006.676

A Framework for the Busy Time Calculation of Multiple Correlated Events

Authors: Simon Schliecker, Matthias Ivers, Jan Staschulat, and Rolf Ernst

Published in: OASIcs, Volume 4, 6th International Workshop on Worst-Case Execution Time Analysis (WCET'06) (2006)

Abstract

Many approaches to determine the response time of a task have difficulty to model tasks with multiple memory or coprocessor accesses with variable access times during the execution. As the request times highly depend on system setup and state, they can not be trivially bounded. If they are bounded by a constant value, large discrepancies between average and worst case make the focus on single worst cases vulnerable to overestimation. We present a novel approach to include remote busy time in the execution time analysis of tasks. We determine the time for multiple requests by a task efficiently and and far less conservative than previous approaches. These requests may be disturbed by other events in the system. We show how to integrate such a multiple event busy time analysis to take into account behavior of tasks that voluntarily suspend themselves and require multiple data from remote parts of the system.

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Simon Schliecker, Matthias Ivers, Jan Staschulat, and Rolf Ernst. A Framework for the Busy Time Calculation of Multiple Correlated Events. In 6th International Workshop on Worst-Case Execution Time Analysis (WCET'06). Open Access Series in Informatics (OASIcs), Volume 4, pp. 1-6, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{schliecker_et_al:OASIcs.WCET.2006.676,
  author =	{Schliecker, Simon and Ivers, Matthias and Staschulat, Jan and Ernst, Rolf},
  title =	{{A Framework for the Busy Time Calculation of Multiple Correlated Events}},
  booktitle =	{6th International Workshop on Worst-Case Execution Time Analysis (WCET'06)},
  pages =	{1--6},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-03-3},
  ISSN =	{2190-6807},
  year =	{2006},
  volume =	{4},
  editor =	{Mueller, Frank},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2006.676},
  URN =		{urn:nbn:de:0030-drops-6767},
  doi =		{10.4230/OASIcs.WCET.2006.676},
  annote =	{Keywords: Response time analysis, multiple memory accesses, multiprocessor, hard real-time, busy time}
}

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Documents authored by Ivers, Matthias

Analysis of Memory Latencies in Multi-Processor Systems

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A Framework for the Busy Time Calculation of Multiple Correlated Events

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